Kostas Adaos

Affiliations:
  • University of Patras, Greece


According to our database1, Kostas Adaos authored at least 11 papers between 1995 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2014
Automated Generation of the Register Set of a SOC and its Verification Environment.
Proceedings of the 18th Panhellenic Conference on Informatics, 2014

2011
Digital baseband challenges for a 60GHz gigabit link.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2008
A Novel System-on-Chip Architecture for Efficient Image Processing.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

2007
Design and Implementation of a Reconfigurable, Embedded Real-Time Face Detection System.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

2006
A core generator for arithmetic cores and testing structures with a network interface.
J. Syst. Archit., 2006

2001
EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001

2000
Development of reusable serial FIR filters with reprogrammable coefficients designed for serial dataflow architectures.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1999
Development of a Reusable E1 Transceiver Suitable for Rapid Prototyping.
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

Efficient implementation of a serial/parallel multiplier for IP based development and rapid prototyping in VLSI digital signal processing.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
An Extensible, Low Cost Rapid Prototyping Environment Based on a Reconfigurable Set of FPGAs.
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

1995
A new efficient dcvs circuit synthesis technique used for an improved implementation of a serial/parallel multiplier.
Int. J. Circuit Theory Appl., 1995


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