Koji Yamazaki

According to our database, Koji Yamazaki authored at least 28 papers between 1991 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

High-definition technology of AI inference scheme for object detection on edge/terminal.

Hiroyuki Uzawa, Shuhei Yoshida, Yukou Iinuma, Saki Hatta, Daisuke Kobayashi, Yuya Omori, Yusuke Horishita, Ken Nakamura, Shuichi Takada, Hassan Toorabally, Koyo Nitta, Koji Yamazaki, Kimikazu Sano

IEICE Electron. Express, 2023

An Estimation Method of Defect Types Using Artificial Neural Networks and Fault Detection Information.

Natsuki Ota, Toshinori Hosokawa, Koji Yamazaki, Yukari Yamauchi, Masayuki Arai

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2021

Attempts Toward Behavior Recognition of the Asian Black Bears Using an Accelerometer.

Kaori Fujinami, Tomoko Naganuma, Yushin Shinoda, Koji Yamazaki, Shinsuke Koike

Proceedings of the Sensor- and Video-Based Activity and Behavior Computing, 2021

2020

Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture.

Yuta Ukon, Koji Yamazaki, Koyo Nitta

IEICE Trans. Commun., 2020

2018

Video Service Function Chaining with a Real-time Packet Reordering Circuit.

Yuta Ukon, Koji Yamazaki, Koyo Nitta

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Flow Cache Cleansing with FPGA Hash Pipe for Highly Stabilized Software Data Plane.

Koji Yamazaki, Yuta Ukon, Shuhei Yoshida, Saki Hatta, Yusuke Sekihara, Shoko Ohteru, Tomoaki Kawamura, Takahiro Hatano, Koyo Nitta, Akihiko Miyazaki

Proceedings of the IEEE 19th International Conference on High Performance Switching and Routing, 2018

2017

A Diagnostic Fault Simulation Method for a Single Universal Logical Fault Model.

Toshinori Hosokawa, Hideyuki Takano, Hiroshi Yamazaki, Koji Yamazaki

Proceedings of the 22nd IEEE Pacific Rim International Symposium on Dependable Computing, 2017

2015

Lagopus FPGA - A reprogrammable data plane for high-performance software SDN switches.

Koji Yamazaki, Yoshihiro Nakajima, Takahiro Hatano, Akihiko Miyazaki

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2014

Accelerating SDN/NFV with Transparent Offloading Architecture.

Koji Yamazaki, Takeshi Osaka, Sadayuki Yasuda, Shoko Ohteru, Akihiko Miyazaki

Proceedings of the Open Networking Summit 2014 - Research Track, 2014

Development of a single cell electroporation method using a scanning ion conductance microscope with a theta type probe pipette.

Satoshi Sakurai, Koji Yamazaki, Tatsuo Ushiki, Futoshi Iwata

Proceedings of the 2014 International Symposium on Micro-NanoMechatronics and Human Science, 2014

2013

A reliable procedure in a new power management technique for a 200-Gbps packet forwarding LSI.

Sadayuki Yasuda, Shoko Ohteru, Yasuyuki Itoh, Koji Yamazaki, Yusuke Sekihara, Takashi Aoki, Masami Urano, Tsugumichi Shibata

IEICE Electron. Express, 2013

Diagnosing Resistive Open Faults Using Small Delay Fault Simulation.

Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hironobu Yotsuyanagi, Masaki Hashizume, Kewal K. Saluja

Proceedings of the 22nd Asian Test Symposium, 2013

2011

A heuristic algorithm for reducing system-level test vectors with high branch coverage.

Koji Yamazaki, Yusuke Sekihara, Takashi Aoki, Eiichi Hosoya, Akira Onozawa

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

Evaluation of transition untestable faults using a multi-cycle capture test generation method.

Masayoshi Yoshimura, Hiroshi Ogawa, Toshinori Hosokawa, Koji Yamazaki

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009

Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC.

Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A Novel Approach for Improving the Quality of Open Fault Diagnosis.

Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

New Class of Tests for Open Faults with Considering Adjacent Lines.

Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information.

Koji Yamazaki, Yuzo Takamatsu

IEICE Trans. Inf. Syst., 2008

Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information.

Yuzo Takamatsu, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Koji Yamazaki

IEICE Trans. Inf. Syst., 2008

Post-BIST Fault Diagnosis for Multiple Faults.

Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato

IEICE Trans. Inf. Syst., 2008

2007

Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines.

Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the 16th Asian Test Symposium, 2007

2006

Effective Post-BIST Fault Diagnosis for Multiple Faults.

Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Fanout-based fault diagnosis for open faults on pass/fail information.

Koji Yamazaki, Yuzo Takamatsu

Proceedings of the 15th Asian Test Symposium, 2006

1999

Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset.

Teruhiko Yamada, Toshinori Kotake, Hiroshi Takahashi, Koji Yamazaki

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1997

An approach to diagnose logical faults in partially observable sequential circuits.

Koji Yamazaki, Teruhiko Yamada

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1995

A Single Bridging Fault Location Technique for CMOS Combinational Circuits.

Koji Yamazaki, Teruhiko Yamada

IEICE Trans. Inf. Syst., 1995

A simple technique for locating gate-level faults in combinational circuits.

Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1991

Method of diagnosing single bridging faults in combinational circuit.

Teruhiko Yamada, Koji Yamazaki

Syst. Comput. Jpn., 1991