Koji Takayanagi

According to our database, Koji Takayanagi authored at least 2 papers between 2013 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM.

Takao Nomura, Ryo Mori, Koji Takayanagi, Kazuki Fukuoka, Koji Nii

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

2013

Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor.

Takao Nomura, Ryo Mori, Munehiro Ito, Koji Takayanagi, Toshihiko Ochiai, Kazuki Fukuoka, Kazuo Otsuga, Koji Nii, Sadayuki Morita, Tomoaki Hashimoto, Tsuyoshi Kida, Junichi Yamada, Hideki Tanaka

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013