Koji Sakui

According to our database, Koji Sakui authored at least 17 papers between 1989 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WoW and CoW to Provide TB/s Bandwidth with Lowest Bit Access Energy.

Norio Chujo, Koji Sakui, Shinji Sugatani, Hiroyuki Ryoson, Tomoji Nakamura, Takayuki Ohba

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

Dynamic Flash Memory with Fast Block Refresh.

Koji Sakui, Masakazu Kakumu, Nozomu Harada

Proceedings of the 20th Non-Volatile Memory Technology Symposium, 2022

2021

Reliability of Wafer-Level Ultra-Thinning down to 3 µm using 20 nm-Node DRAMs.

Zhwen Chen, Young-Suk Kim, Tadashi Fukuda, Koji Sakui, Takayuki Ohba, Tatsuji Kobayashi, Takashi Obara

Proceedings of the IEEE International Reliability Physics Symposium, 2021

Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT).

Koji Sakui, Nozomu Harada

Proceedings of the IEEE International Memory Workshop, 2021

1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar.

Yisuo Li, Ken'ichi Kanazawa, Tetsuo Izawa, Koji Sakui, Georg Strof, Oskar Baumgartner, Gerhard Rzepa, Markus Karner, Zlatan Stanojevic, Nozomu Harada, Fujio Masuoka

Proceedings of the IEEE International Memory Workshop, 2021

2019

Three-dimensional Integration (3DI) with Bumpless Interconnects for Tera-scale Generation : High Speed, Low Power, and Ultra-small Operating Platform.

Koji Sakui, Takayuki Ohba

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN) with the Bumpless TSV Technology.

Koji Sakui, Takayuki Ohba

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2010

Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET.

Tetsuo Endoh, Koji Sakui, Yukio Yasuda

IEICE Trans. Electron., 2010

Design of 30 nm FinFETs and Double Gate MOSFETs with Halo Structure.

Tetsuo Endoh, Koji Sakui, Yukio Yasuda

IEICE Trans. Electron., 2010

A compact and low power logic design for multi-pillar vertical MOSFETs.

Koji Sakui, Tetsuo Endoh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2000

A source-line programming scheme for low-voltage operation NAND flash memories.

Ken Takeuchi, Shinji Satoh, Ken-ichi Imamiya, Koji Sakui

IEEE J. Solid State Circuits, 2000

1999

A negative V_th cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories.

Ken Takeuchi, Shinji Satoh, Tomoharu Tanaka, Ken-ichi Imamiya, Koji Sakui

IEEE J. Solid State Circuits, 1999

A 130-mm/², 256-Mbit NAND flash with shallow trench isolation technology.

Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, Koji Sakui

IEEE J. Solid State Circuits, 1999

A CMOS bandgap reference circuit with sub-1-V operation.

Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru Tanzawa, Shigeru Atsumi, Koji Sakui

IEEE J. Solid State Circuits, 1999

1997

A 120-mm² 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed.

Jin-Ki Kim, Koji Sakui, Sung-Soo Lee, Yasuo Itoh, Suk-Chon Kwon, Kazuhisa Kanazawa, Ki-Jun Lee, Hiroshi Nakamura, Kang-Young Kim, Toshihiko Himeno, Jang-Rae Kim, Kazushige Kanda, Tae-Sung Jung, Yoichi Oshima, Kang-Deog Suh, Kazuhiko Hashimoto, Sung-Tae Ahn, Junichi Miyamoto

IEEE J. Solid State Circuits, 1997

1994

A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory.

Tomoharu Tanaka, Yoshiyuki Tanaka, Hiroshi Nakamura, Koji Sakui, Hideko Oodaira, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka, Hisashi Hara

IEEE J. Solid State Circuits, November, 1994

1989

An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode.

Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka

IEEE J. Solid State Circuits, June, 1989