Koji Kishimoto
According to our database1,
Koji Kishimoto
authored at least 3 papers
between 1997 and 2011.
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Bibliography
2011
Proceedings of the Ubiquitous Intelligence and Computing - 8th International Conference, 2011
2010
Proceedings of the 28th International Conference on Human Factors in Computing Systems, 2010
1997
A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O.
IEEE J. Solid State Circuits, 1997