Koji Hirairi

According to our database, Koji Hirairi authored at least 10 papers between 2005 and 2018.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2018

Session 18 overview: Adaptive circuits and digital regulators: Digital circuit techniques subcommittee.

Dennis Sylvester, Koji Hirairi, Edith Beigné

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2013

Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V_DDmin-Aware Dual Supply Voltage Technique.

Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

IEEE Trans. Very Large Scale Integr. Syst., 2013

2012

13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO.

Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V_DDmin limited ultra low voltage logic circuits.

Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011

Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS.

Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V_DD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated V_DD between flip-flops and combinational logics.

Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

2010

Misleading energy and performance claims in sub/near threshold digital systems.

Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2007

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.

Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata

IBM J. Res. Dev., 2007

2006

Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor.

James D. Warnock, Dieter F. Wendel, Tony Aipperspach, Erwin Behnen, Robert A. Cordes, Sang H. Dhong, Koji Hirairi, Hiroaki Murakami, Shohji Onishi, Dac C. Pham, Jürgen Pille, Stephen D. Posluszny, Osamu Takahashi, Huajun Wen

IEEE J. Solid State Circuits, 2006

2005

The circuit design of the synergistic processor element of a CELL processor.

Osamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005