Koji Arai

According to our database, Koji Arai authored at least 4 papers between 2001 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

The Introduction Case and Effect of "Robot Design" for Object Lesson of Mechanical Engineer.

Hajime Aoyama, Kazutaka Yokota, Kazuyoshi Ishikawa, Saori Ishimura, Junya Seki, Yoshinori Adachi, Yuichi Satsumi, Asami Takahashi, Yoji Ishimaru, Nobushige Imai, Yoshinao Okamura, Itsuo Nishihara, Koji Arai

J. Robotics Mechatronics, 2011

2005

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer.

Hiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi

IEEE J. Solid State Circuits, 2005

2003

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer.

Tatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama

IEEE J. Solid State Circuits, 2003

2001

A multigigabit DRAM technology with 6F² open-bitline cell, distributed overdriven sensing, and stacked-flash fuse.

Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh

IEEE J. Solid State Circuits, 2001