Koichi Seki

According to our database, Koichi Seki authored at least 10 papers between 1990 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2014

Vehicles as Information Hubs During Disasters: Glueing Wi-Fi to TV White Space to Cellular Networks.

Onur Altintas, Koichi Seki, Haris Kremo, Makiko Matsumoto, Ryokichi Onishi, Hideaki Tanaka

IEEE Intell. Transp. Syst. Mag., 2014

1999

Single-electron memory for giga-to-tera bit storage.

Kazuo Yano, Tomoyuki Ishii, Toshiaki Sano, Toshiyuki Mine, Fumio Murai, Takashi Hashimoto, Takashi Kobayashi, Tokuo Kure, Koichi Seki

Proc. IEEE, 1999

1997

Instruction buffering to reduce power in processors for signal processing.

Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki

IEEE Trans. Very Large Scale Integr. Syst., 1997

1996

Top-down pass-transistor logic design.

Kazuo Yano, Yasuhiko Sasaki, Kunihito Rikino, Koichi Seki

IEEE J. Solid State Circuits, 1996

Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer.

Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1993

Low-voltage ULSI design.

Katsuhiro Shimohigashi, Koichi Seki

IEEE J. Solid State Circuits, April, 1993

1992

A 1.5-V full-swing BiCMOS logic circuit.

Mitsuru Hiraki, Kazuo Yano, Masataka Minami, Kazushige Sato, Nozomu Matsuzaki, Atsuo Watanabe, Takashi Nishida, Katsuro Sasaki, Koichi Seki

IEEE J. Solid State Circuits, November, 1992

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules.

Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, M. Hanawa, Masato Suzuki, S. Morita, A. Kawamata, Nagatoshi Ohki, Takashi Nishida, Koichi Seki

IEEE J. Solid State Circuits, March, 1992

1991

Quasi-complementary BiCMOS for sub-3-V digital circuits.

Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Yasuo Onose, Mitsuru Hirao, Nagatoshi Ohki, Takashi Nishida, Koichi Seki, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, November, 1991

1990

An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller.

Koichi Seki, Hitoshi Kume, Yuzuru Ohji, Takashi Kobayashi, Atushi Hiraiwa, Takeshi Nishida, Takeshi Wada, Kazuhiro Komori, Kazuto Izawa, Toshiaki Nishimoto, Yasuroh Kubota, Kazuyoshi Shoji

IEEE J. Solid State Circuits, October, 1990