Kohji Hosokawa

Orcid: 0009-0009-8086-8144

According to our database1, Kohji Hosokawa authored at least 17 papers between 1998 and 2023.

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Bibliography

2023
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh.
IEEE Trans. Very Large Scale Integr. Syst., 2023

An analog-AI chip for energy-efficient speech recognition and transcription.
Nat., 2023

Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited).
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Pattern Training, Inference, and Regeneration Demonstration Using On-Chip Trainable Neuromorphic Chips for Spiking Restricted Boltzmann Machine.
Adv. Intell. Syst., 2022

Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Analysis of Effect of Weight Variation on SNN Chip with PCM-Refresh Method.
Neural Process. Lett., 2021

Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2019
AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed.
IBM J. Res. Dev., 2019

Training Large-Scale Spiking Neural Networks on Multi-core Neuromorphic System Using Backpropagation.
Proceedings of the Neural Information Processing - 26th International Conference, 2019

Performance Analysis of Spiking RBM with Measurement-Based Phase Change Memory Model.
Proceedings of the Neural Information Processing - 26th International Conference, 2019

2018
NVM Weight Variation Impact on Analog Spiking Neural Network Chip.
Proceedings of the Neural Information Processing - 25th International Conference, 2018

2017
Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory.
IBM J. Res. Dev., 2017

Neuromorphic devices and architectures for next-generation cognitive computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2003
A low power CMOS circuit with Variable Souce Scheme (VSCMOS).
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

1998
A 220-mm<sup>2</sup>, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture.
IEEE J. Solid State Circuits, 1998


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