Kohei Miyase

According to our database, Kohei Miyase authored at least 77 papers between 2001 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Fault Resilience Techniques for Flash Memory of DNN Accelerators.

Shyue-Kung Lu, Yu-Sheng Wu, Jin-Hua Hong, Kohei Miyase

Proceedings of the IEEE International Test Conference, 2022

Fine-Grained Built-In Self-Repair Techniques for NAND Flash Memories.

Shyue-Kung Lu, Shi-Chun Tseng, Kohei Miyase

Proceedings of the IEEE International Test Conference, 2022

A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications.

Kazuya Loki, Yasuyuki Kai, Kohei Miyase, Seiji Kajihara

Proceedings of the IEEE International Test Conference, 2022

Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits.

Taiki Utsunomiya, Ryu Hoshino, Kohei Miyase, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara

Proceedings of the IEEE International Test Conference in Asia, 2022

2021

On the Efficacy of Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption.

Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian

IEICE Trans. Inf. Syst., 2021

Fault-Aware Dependability Enhancement Techniques for Phase Change Memory.

Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase, Chun-Lung Hsu, Chi-Tien Sun

J. Electron. Test., 2021

2020

Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments.

Aibin Yan, Xiangfeng Feng, Yuanjie Hu, Chaoping Lai, Jie Cui, Zhili Chen, Kohei Miyase, Xiaoqing Wen

IEEE Trans. Aerosp. Electron. Syst., 2020

Analyzing Running Form with Acceleration Sensor.

Chihiro Koga, Kohei Miyase, Masato Tokui

Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020

2019

Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM.

Shyue-Kung Lu, Hung-Kai Huang, Chun-Lung Hsu, Chi-Tien Sun, Kohei Miyase

J. Electron. Test., 2019

A Static Method for Analyzing Hotspot Distribution on the LSI.

Kohei Miyase, Yudai Kawano, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara

Proceedings of the IEEE International Test Conference in Asia, 2019

2018

Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory.

Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing.

Yucong Zhang, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Hans-Joachim Wunderlich, Jun Qian

Proceedings of the 27th IEEE Asian Test Symposium, 2018

Progressive ECC Techniques for Phase Change Memory.

Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Analysis and mitigation or IR-Drop induced scan shift-errors.

Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen

Proceedings of the IEEE International Test Conference, 2017

Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption.

Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation.

Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

SAT-based post-processing for regional capture power reduction in at-speed scan test generation.

Stephan Eggersglüß, Kohei Miyase, Xiaoqing Wen

Proceedings of the 21th IEEE European Test Symposium, 2016

On Optimal Power-Aware Path Sensitization.

Matthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker, Ilia Polian

Proceedings of the 25th IEEE Asian Test Symposium, 2016

Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test.

Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

A soft-error tolerant TCAM using partial don't-care keys.

Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase

Proceedings of the 20th IEEE European Test Symposium, 2015

Identification of high power consuming areas with gate type and logic level information.

Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara

Proceedings of the 20th IEEE European Test Symposium, 2015

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch.

Koji Asada, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jun Qian

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.

Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang

IEICE Trans. Inf. Syst., 2014

Soft-error tolerant TCAMs for high-reliability packet classifications.

Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Scan-Out Power Reduction for Logic BIST.

Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase

IEICE Trans. Inf. Syst., 2013

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing.

Kohei Miyase, Ryota Sakai, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara

IEICE Trans. Inf. Syst., 2013

LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing.

Yuta Yamato, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen, Laung-Terng Wang, Michael A. Kochte

IEEE Des. Test, 2013

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression.

Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Search Space Reduction for Low-Power Test Generation.

Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara

Proceedings of the 22nd Asian Test Symposium, 2013

2012

A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits.

Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

On pinpoint capture power management in at-speed scan test generation.

Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang

Proceedings of the 2012 IEEE International Test Conference, 2012

A Scan-Out Power Reduction Method for Multi-cycle BIST.

Senling Wang, Yasuo Sato, Kohei Miyase, Seiji Kajihara

Proceedings of the 21st IEEE Asian Test Symposium, 2012

Low Power BIST for Scan-Shift and Capture Power.

Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

A GA-Based <i>X</i>-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing.

Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara

IEICE Trans. Inf. Syst., 2011

Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing.

Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara

IEICE Trans. Inf. Syst., 2011

Power-aware test generation with guaranteed launch safety for at-speed scan testing.

Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

A novel scan segmentation design method for avoiding shift timing failure in scan testing.

Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang

Proceedings of the 2011 IEEE International Test Conference, 2011

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures.

Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Transition-Time-Relation based capture-safety checking for at-speed scan test generation.

Kohei Miyase, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara

Proceedings of the Design, Automation and Test in Europe, 2011

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling.

Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Efficient BDD-based Fault Simulation in Presence of Unknown Values.

Michael A. Kochte, Sandip Kundu, Kohei Miyase, Xiaoqing Wen, Hans-Joachim Wunderlich

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Power-Aware Test Pattern Generation for At-Speed LOS Testing.

Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, Xiaoqing Wen

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

On Delay Test Quality for Test Cubes.

Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen

IPSJ Trans. Syst. LSI Des. Methodol., 2010

A Study of Capture-Safe Test Generation Flow for At-Speed Testing.

Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.

Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor

IEICE Trans. Inf. Syst., 2010

Is test power reduction through X-filling good enough?

Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed

Proceedings of the 2011 IEEE International Test Conference, 2010

On estimation of NBTI-Induced delay degradation.

Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura

Proceedings of the 15th European Test Symposium, 2010

2009

Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment.

Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing.

Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment.

Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing.

Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, Masao Aso, Hiroshi Furukawa

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

A Novel Per-Test Fault Diagnosis Method Based on the Extended <i>X</i>-Fault Model for Deep-Submicron LSI Circuits.

Yuta Yamato, Yusuke Nakamura, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara

IEICE Trans. Inf. Syst., 2008

On Detection of Bridge Defects with Stuck-at Tests.

Kohei Miyase, Kenta Terashima, Xiaoqing Wen, Seiji Kajihara, Sudhakar M. Reddy

IEICE Trans. Inf. Syst., 2008

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.

Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita

J. Electron. Test., 2008

Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing.

Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase

Proceedings of the 2008 IEEE International Test Conference, 2008

Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification.

Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing.

Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja

Proceedings of the 13th European Test Symposium, 2008

Diagnosis of Realistic Defects Based on the X-Fault Model.

Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.

Hiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

A Novel ATPG Method for Capture Power Reduction during Scan Testing.

Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita

IEICE Trans. Inf. Syst., 2007

A novel scheme to reduce power supply noise for high-quality at-speed scan testing.

Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang

Proceedings of the 2007 IEEE International Test Conference, 2007

Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing.

Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja

Proceedings of the 44th Design Automation Conference, 2007

2006

A Per-Test Fault Diagnosis Method Based on the <i>X</i>-Fault Model.

Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita

IEICE Trans. Inf. Syst., 2006

A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.

Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.

Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005

Efficient Test Set Modification for Capture Power Reduction.

Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja

J. Low Power Electron., 2005

On Improving Defect Coverage of Stuck-at Fault Tests.

Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

XID: Don't care identification of test patterns for combinational circuits.

Kohei Miyase, Seiji Kajihara

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Don't Care Identification and Statistical Encoding for Test Data Compression.

Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy

IEICE Trans. Inf. Syst., 2004

Multiple Scan Tree Design with Test Vector Modification.

Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

On test data volume reduction for multiple scan chain designs.

Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz

ACM Trans. Design Autom. Electr. Syst., 2003

Optimal Scan Tree Construction with Test Vector Modification for Test Compression.

Kohei Miyase, Seiji Kajihara

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Test Vector Modification for Power Reduction during Scan Testing.

Seiji Kajihara, Koji Ishida, Kohei Miyase

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Don't-Care Identification on Specific Bits of Test Patterns.

Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

A Method of Static Test Compaction Based on Don't Care Identification.

Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Test Data Compression Using Don?t-Care Identification and Statistical Encoding.

Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits.

Seiji Kajihara, Kohei Miyase

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001