Koh Johguchi
According to our database1,
Koh Johguchi
authored at least 21 papers
between 2003 and 2023.
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Bibliography
2023
Photodiode and Analog-Front-End Circuit Design for Wearable Vital Sensing System with Fiber-Bragg-Grating Sensor.
Proceedings of the International Symposium on Devices, Circuits and Systems, 2023
Proceedings of the International Symposium on Devices, Circuits and Systems, 2023
2020
A Smart Hybrid Solid-State-Drive Storage System based on Nonvolatile Storage-Class-Memories : Device, Circuit Design and Architecture.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020
2019
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
2018
2016
Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive.
IEEE Trans. Very Large Scale Integr. Syst., 2016
2014
A High Performance and Energy-Efficient Cold Data Eviction Algorithm for 3D-TSV Hybrid ReRAM/MLC NAND SSD.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
NAND Phase Change Memory with Block Erase Architecture and Pass-Transistor Design Requirements for Write and Disturbance.
IEICE Trans. Electron., 2014
A Temperature Tracking Read Reference Current and Write Voltage Generator for Multi-Level Phase Change Memories.
IEICE Trans. Electron., 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
2013
Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppression.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression.
Proceedings of the Symposium on VLSI Circuits, 2012
2011
Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design.
IEICE Trans. Electron., 2011
A 3D-Integration method to compensate output voltage degradation of boost converter for compact Solid-State-Drives.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
2007
4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words.
IEICE Trans. Electron., 2007
A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin.
IEICE Electron. Express, 2007
A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2003