Koen Goetschalckx
Orcid: 0000-0002-5713-9332
According to our database1,
Koen Goetschalckx
authored at least 9 papers
between 2017 and 2024.
Collaborative distances:
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Bibliography
2024
11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
DepFiN: A 12-nm Depth-First, High-Resolution CNN Processor for IO-Efficient Inference.
IEEE J. Solid State Circuits, May, 2023
DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
2022
DeFiNES: A DSE Framework Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators.
Dataset, November, 2022
2021
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Efficiently Combining SVD, Pruning, Clustering and Retraining for Enhanced Neural Network Compression.
Proceedings of the 2nd International Workshop on Embedded and Mobile Deep Learning, 2018
2017
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017