Ko Yoshikawa

According to our database, Ko Yoshikawa authored at least 10 papers between 1991 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator".

Tao Li, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh

IEEE Trans. Very Large Scale Integr. Syst., June, 2023

Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator.

Tao Li, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh

IEEE Trans. Very Large Scale Integr. Syst., 2023

2022

Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT.

Tao Li, Yitao Ma, Ko Yoshikawa, Osamu Nomura, Tetsuo Endoh

IEEE Trans. Ind. Informatics, 2022

2006

Domino Logic Synthesis System and its Applications.

Ko Yoshikawa, Shigeto Inui, Yasuhiko Hagihara, Yuichi Nakamura, Takeshi Yoshimura

J. Circuits Syst. Comput., 2006

Budgeting-free hierarchical design method for large scale and high-performance LSIs.

Yuichi Nakamura, Mitsuru Tagata, Takumi Okamoto, Shigeyoshi Tawada, Ko Yoshikawa

Proceedings of the 43rd Design Automation Conference, 2006

2005

An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs.

Yuichi Nakamura, Ko Yoshikawa, Takeshi Yoshimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

2004

A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication.

Yuichi Nakamura, Kohei Hosokawa, Ichiro Kuroda, Ko Yoshikawa, Takeshi Yoshimura

Proceedings of the 41th Design Automation Conference, 2004

Timing optimization by replacing flip-flops to latches.

Ko Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura, Shigeto Inui, Takeshi Yoshimura

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

1999

Logic Synthesizer with Optimizations in Two Phases.

Ko Yoshikawa, Saburo Muroga

Proceedings of the VLSI Handbook., 1999

1991

Timing Optimization on Mapped Circuits.

Ko Yoshikawa, Hiroshi Ichiryu, Hisato Tanishita, Shigenobu Suzuki, Nobuyoshi Nomizu, Akira Kondoh

Proceedings of the 28th Design Automation Conference, 1991