Ko-Chi Kuo

According to our database, Ko-Chi Kuo authored at least 32 papers between 2006 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

A three reference voltage 0.5V 10-bit SAR-ADC using merge split capacitor switching scheme in 40nm CMOS.

Ko-Chi Kuo, Sin-Cong Huang, Chun-Wei Huang

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2024

A 10-bit 300MS/s Time-Interleaved Successive-Approximation Register Analog-to-Digital Converter with a Binary-Scaled Recombination Weighting Capacitor Array and fault-tolerant.

Ko-Chi Kuo, Hung-Yi Chang, Chun-Wei Huang

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2024

2023

A 12-bit 1GS/s Digital to Analog Converter with Switching-Minimized Monotonic Coding.

Ko-Chi Kuo, Shih-En Huang, Hong-Yi Liao

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

An Area Efficient Analog Front-End for Sensing EEG Signals with MOS Capacitors in 90nm Process.

Ko-Chi Kuo, Chao-Tung Chen, Hong-Yi Liao

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

2022

A 8-bit 300MHz Domino Based Successive Approximation Register ADC.

Ko-Chi Kuo, Hsiung-Yu Chi

Proceedings of the 19th International SoC Design Conference, 2022

A 12-bit 1 GS/s Current Steering DAC with the Appointed and Thermometer Coding Scheme.

Ko-Chi Kuo, Ying-Ju Sung

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

A Novel Linear-Logarithmic Active Pixel CMOS Image Sensor with wide dynamic range.

Ko-Chi Kuo

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A Fast Locking All Digital Delay Locked Loop with wide operating frequency ranged from 0.5 GHz to 1.8 GHz in 40nm Process.

Ko-Chi Kuo

Proceedings of the 18th International SoC Design Conference, 2021

2019

A 10-bit 250 MS/s Binary Search and Two channel SAR ADC by a two-bit per Conversion with Error Tolerance Ability.

Ko-Chi Kuo

Proceedings of the 2019 International SoC Design Conference, 2019

A High Speed Low Power Pipelined SAR Analog to Digital Converter.

Ko-Chi Kuo

Proceedings of the International Conference on IC Design and Technology, 2019

Fast Locking Technique by Using a Programmable Operational Transconductor for a Phase Lock Loop Design.

Ko-Chi Kuo

Proceedings of the International Conference on IC Design and Technology, 2019

A Bio-Sensing System-on-Chip and Software for Smart Clothes.

Hsu-Kang Dow, Ing-Jer Huang, Robert Rieger, Ko-Chi Kuo, Lan-Yuen Guo, Shih-Jung Pao

Proceedings of the IEEE International Conference on Consumer Electronics, 2019

2016

The implementation of HomePlug AV system.

Ko-Chi Kuo

Proceedings of the International Conference on IC Design and Technology, 2016

2015

Power saving technique for thermometer-code digital-to-analog converters.

Ko-Chi Kuo, Chih-Wei Wu

Proceedings of the 15th International Symposium on Communications and Information Technologies, 2015

A wide-range and harmonic-free SAR all-digital delay locked loop.

Ko-Chi Kuo, Sz-Hsien Li

Proceedings of the 15th International Symposium on Communications and Information Technologies, 2015

2014

A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX.

Ko-Chi Kuo, Chi-Wei Wu

Expert Syst. Appl., 2014

2012

A 120-420 MHz delay-locked loop with multi-band voltage-controlled delay unit.

Ko-Chi Kuo, Yi-Hsi Hsu

Int. J. Circuit Theory Appl., 2012

Low power design flow with static and statistical timing analysis.

Ko-Chi Kuo, Hsueh-Ta Ko

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

Power line communication chip design with data error detecting/correcting and data encrypting/decrypting ability.

Ko-Chi Kuo, Hsun-Chia Hsu

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

High linear transconductor for multiband CMOS receiver.

Ko-Chi Kuo, Shan-Yu Chen, Shih-Min Tseng

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

Low power delay locked loop with all digital controlled SAR delay cell.

Ko-Chi Kuo, Chung-Yuan Chang, Si-Hsien Li

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

A Switching Sequence for Linear Gradient Error Compensation in the DAC Design.

Ko-Chi Kuo, Chi-Wei Wu

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 2.4GHz low phase noise frequency synthesizer for WiMAX applications.

Ko-Chi Kuo

IEICE Electron. Express, 2011

2010

Low power and high speed multiplier design with row bypassing and parallel architecture.

Ko-Chi Kuo, Chi-Wen Chou

Microelectron. J., 2010

A fully digital modulator/demodulator for Power Line Communication (PLC).

Ko-Chi Kuo, Jia-Wei Guo, Yu-Hao Ou

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Low power level shifter and combined with logic gates.

Ko-Chi Kuo, Sheng-Quane Chen

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

A low voltage, high linear, and tunable triode transconductor.

Ko-Chi Kuo, Hsing-Hui Wu

IEICE Electron. Express, 2009

2008

5 GHz phase locked loop with auto band selection.

Ko-Chi Kuo, Ming-Jing Chen

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2006

A CMOS High-Speed Nine-Stage Programmable Counter.

Ko-Chi Kuo, Feng-Ji Wu

Proceedings of the International MultiConference of Engineers and Computer Scientists 2006, 2006

A Low-Power Multiplier with Bypassing Logic and Operand Decomposition.

Ko-Chi Kuo, Chi-Wen Chou

Proceedings of the International MultiConference of Engineers and Computer Scientists 2006, 2006

A 2.4-GHz/5-GHz Low Power Pulse Swallow Counter in 0.18-µm CMOS Technology.

Ko-Chi Kuo, Feng-Ji Wu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Low Power Multiplier with Bypassing and Tree Strucuture.

Ko-Chi Kuo, Chi-Wen Chou

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006