Klaas Bult

Orcid: 0000-0002-4757-4250

According to our database1, Klaas Bult authored at least 28 papers between 1988 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2014, "For contributions to the design of high frequency analog and mixed signal circuits".

Timeline

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Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A Resistive Degeneration Technique for Linearizing Open-Loop Amplifiers.
IEEE Trans. Circuits Syst., 2020

2018
A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers.
IEEE J. Solid State Circuits, 2018

A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier.
IEEE J. Solid State Circuits, 2018

A Capacitively Degenerated 100-dB Linear 20-150 MS/s Dynamic Amplifier.
IEEE J. Solid State Circuits, 2018

2017
A 13mW 64dB SNDR 280MS/s pipelined ADC using linearized open-loop class-AB amplifiers.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2015
A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration.
IEEE J. Solid State Circuits, 2015

26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOS.
IEEE J. Solid State Circuits, 2014

8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration.
Proceedings of the ESSCIRC 2014, 2014

Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3 < -58 dBc in 40 nm CMOS.
IEEE J. Solid State Circuits, 2013

2011
An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS.
IEEE J. Solid State Circuits, 2011

An 800MS/s dual-residue pipeline ADC in 40nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009
A 12 bit 2.9 GS/s DAC With IM3 ≪ -60 dBc Beyond 1 GHz in 65 nm CMOS.
IEEE J. Solid State Circuits, 2009

A 12b 2.9GS/s DAC with IM3 ≪-60dBc beyond 1GHz in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Embedded analog-to-digital converters.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2004
A 21-mW 8-b 125-MSample/s ADC in 0.09-mm<sup>2</sup> 0.13-μm CMOS.
IEEE J. Solid State Circuits, 2004

1999
A single-chip universal digital satellite receiver with 480-MHz IF input.
IEEE J. Solid State Circuits, 1999

1998
A 10-b, 500-MSample/s CMOS DAC in 0.6 mm<sup>2</sup>.
IEEE J. Solid State Circuits, 1998

Design considerations for gigabit Ethernet 1000Base-T twisted pair transceivers.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997
An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm<sup>2</sup>.
IEEE J. Solid State Circuits, 1997

1992
An inherently linear and compact MOST-only current division technique.
IEEE J. Solid State Circuits, December, 1992

1990
A fast-settling CMOS op amp for SC circuits with 90-dB DC gain.
IEEE J. Solid State Circuits, December, 1990

1989
Design and analysis of CMOS analog signal processing circuits by means of a graphical MOST model.
IEEE J. Solid State Circuits, June, 1989

1988
A CMOS analog continuous-time delay line with adaptive delay-time control.
IEEE J. Solid State Circuits, June, 1988


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