Kiyotaka Imai

According to our database, Kiyotaka Imai authored at least 5 papers between 1995 and 2005.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2005

Device technology for body biasing scheme.

Kiyotaka Imai, Yasushi Yamagata, Sadaaki Masuoka, Naohiko Kimuzuka, Yuri Yasuda, Mitsuhiro Togo, Masahiro Ikeda, Yasutaka Nakashiba

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2001

A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO.

Koichiro Minami, Muneo Fukaishi, Masayuki Mizuno, Hideaki Onishi, Kenji Noda, Kiyotaka Imai, Tadahiko Horiuchi, Hiroshi Yamaguchi, Takanori Sato, Kazuyuki Nakamura, Masakazu Yaniashina

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

1998

A unified MOSFET channel charge model for device modeling in circuit simulation.

Yuhua Cheng, Kai Chen, Kiyotaka Imai, Chenming Hu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1996

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump.

Hitoshi Okamura, Takao Atsumo, Koichi Takeda, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Tom Yamazaki

IEEE J. Solid State Circuits, 1996

1995

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors.

Hitoshi Okamura, Hideo Toyoshima, Koichi Takeda, Takashi Oguri, Satoshi Nakamura, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Hiroshi Yoshida, Tom Yamazaki

IEEE J. Solid State Circuits, November, 1995