Kiyoshi Hayase
According to our database1,
Kiyoshi Hayase
authored at least 4 papers
between 1997 and 2008.
Collaborative distances:
Collaborative distances:
Timeline
1998
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2004
2006
2008
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2008
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2004
A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory.
IEEE J. Solid State Circuits, 2004
1997
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997