Kiyoharu Hamaguchi
According to our database1,
Kiyoharu Hamaguchi
authored at least 26 papers
between 1990 and 2023.
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Bibliography
2023
Parallelizing Random and SAT-based Verification Processes for Improving Toggle Coverage.
IPSJ Trans. Syst. LSI Des. Methodol., 2023
2019
2018
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
Extracting hardware assertions including word-level relations over multiple clock cycles.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
2011
IPSJ Trans. Syst. LSI Des. Methodol., 2011
2010
Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic.
IPSJ Trans. Syst. LSI Des. Methodol., 2010
IPSJ Trans. Syst. LSI Des. Methodol., 2010
2009
IPSJ Trans. Syst. LSI Des. Methodol., 2009
2007
Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
2006
Expressive Power of Quantum Pushdown Automata with Classical Stack Operations under the Perfect-Soundness Condition.
IEICE Trans. Inf. Syst., 2006
2005
Automatic monitor generation from regular expression based specifications for module interface verification.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
Symbolic Simulation Heuristics for High-Level Hardware Descriptions Including Uninterpreted Functions.
IEICE Trans. Inf. Syst., 2004
Validity Checking for Quantifier-Free First-Order Logic with Equality Using Substitution of Boolean Formulas.
Proceedings of the Automated Technology for Verification and Analysis: Second International Conference, 2004
2001
Symbolic simulation heuristics for high-level design descriptions with uninterpreted functions.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001
2000
Proceedings of the Formal Methods in Computer-Aided Design, Third International Conference, 2000
Ordered Quantum Branching Programs Are More Powerful than Ordered Probabilistic Branching Programs under a Bounded-Width Restriction.
Proceedings of the Computing and Combinatorics, 6th Annual International Conference, 2000
1997
1995
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
1993
The Complexity of the Optimal Variable Ordering Problems of Shared Binary Decision Diagrams.
Proceedings of the Algorithms and Computation, 4th International Symposium, 1993
1992
Theor. Comput. Sci., 1992
Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992
1991
Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification.
Proceedings of the Computer Aided Verification, 3rd International Workshop, 1991
Formal Verification of Speed-Dependent Asynchronous Cicuits Using Symbolic Model Checking of branching Time Regular Temporal Logic.
Proceedings of the Computer Aided Verification, 3rd International Workshop, 1991
1990
Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990
Branching Time Regular Temporal Logic for Model Checking with Linear Time Complexity.
Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990