Kiyoharu Hamaguchi

According to our database, Kiyoharu Hamaguchi authored at least 26 papers between 1990 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Parallelizing Random and SAT-based Verification Processes for Improving Toggle Coverage.

Kiyoharu Hamaguchi

IPSJ Trans. Syst. LSI Des. Methodol., 2023

2019

Foreword.

Kiyoharu Hamaguchi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

2018

Applying an SMT Solver to Coverage-Driven Design Verification.

Kiyoharu Hamaguchi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Extracting hardware assertions including word-level relations over multiple clock cycles.

Mami Miyamoto, Kiyoharu Hamaguchi

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

2017

Coverage-Driven Design Verification Using a Diverse SAT Solver.

Yosuke Kakiuchi, Kiyoharu Hamaguchi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2011

Symbolic Discord Computation for Efficient Analysis of Message Sequence Charts.

Yosuke Kakiuchi, Tomofumi Nakagawa, Kiyoharu Hamaguchi, Tadaaki Tanimoto, Masaki Nakanishi

IPSJ Trans. Syst. LSI Des. Methodol., 2011

2010

Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic.

Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara

IPSJ Trans. Syst. LSI Des. Methodol., 2010

Approximate Model Checking Using a Subset of First-order Logic.

Kiyoharu Hamaguchi, Kazuya Masuda, Toshinobu Kashiwabara

IPSJ Trans. Syst. LSI Des. Methodol., 2010

2009

Checker Generation of Assertions with Local Variables for Model Checking.

Sho Takeuchi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara

IPSJ Trans. Syst. LSI Des. Methodol., 2009

2007

Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints.

Hiroaki Kozawa, Kiyoharu Hamaguchi, Toshinobu Kashiwabara

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006

Expressive Power of Quantum Pushdown Automata with Classical Stack Operations under the Perfect-Soundness Condition.

Masaki Nakanishi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara

IEICE Trans. Inf. Syst., 2006

2005

Automatic monitor generation from regular expression based specifications for module interface verification.

Yosuke Kakiuchi, A. Kitajima, Kiyoharu Hamaguchi, Toshinobu Kashiwabara

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Symbolic Simulation Heuristics for High-Level Hardware Descriptions Including Uninterpreted Functions.

Kiyoharu Hamaguchi

IEICE Trans. Inf. Syst., 2004

Validity Checking for Quantifier-Free First-Order Logic with Equality Using Substitution of Boolean Formulas.

Atsushi Moritomo, Kiyoharu Hamaguchi, Toshinobu Kashiwabara

Proceedings of the Automated Technology for Verification and Analysis: Second International Conference, 2004

2001

Symbolic simulation heuristics for high-level design descriptions with uninterpreted functions.

Kiyoharu Hamaguchi

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

2000

Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs.

Kiyoharu Hamaguchi, Hidekazu Urushihara, Toshinobu Kashiwabara

Proceedings of the Formal Methods in Computer-Aided Design, Third International Conference, 2000

Ordered Quantum Branching Programs Are More Powerful than Ordered Probabilistic Branching Programs under a Bounded-Width Restriction.

Masaki Nakanishi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara

Proceedings of the Computing and Combinatorics, 6th Annual International Conference, 2000

1997

Another Look at LTL Model Checking.

Edmund M. Clarke, Orna Grumberg, Kiyoharu Hamaguchi

Formal Methods Syst. Des., 1997

1995

Efficient construction of binary moment diagrams for verifying arithmetic circuits.

Kiyoharu Hamaguchi, Akihito Morita, Shuzo Yajima

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1993

The Complexity of the Optimal Variable Ordering Problems of Shared Binary Decision Diagrams.

Seiichiro Tani, Kiyoharu Hamaguchi, Shuzo Yajima

Proceedings of the Algorithms and Computation, 4th International Symposium, 1993

1992

Infinity-Regular Temporal Logic and its Model Checking Problem.

Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima

Theor. Comput. Sci., 1992

Design Verification of a Microprocessor Using Branching Time Regular Temporal Logic.

Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima

Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992

1991

Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification.

Hiromi Hiraishi, Kiyoharu Hamaguchi, Hiroyuki Ochi, Shuzo Yajima

Proceedings of the Computer Aided Verification, 3rd International Workshop, 1991

Formal Verification of Speed-Dependent Asynchronous Cicuits Using Symbolic Model Checking of branching Time Regular Temporal Logic.

Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima

Proceedings of the Computer Aided Verification, 3rd International Workshop, 1991

1990

Vectorized Model Checking for Computation Tree Logic.

Hiromi Hiraishi, Shintaro Meki, Kiyoharu Hamaguchi

Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990

Branching Time Regular Temporal Logic for Model Checking with Linear Time Complexity.

Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima

Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990