Kiyeon Lee

According to our database1, Kiyeon Lee authored at least 10 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2023
Scattering and Nonscattering of the Hartree-Type Nonlinear Dirac System at Critical Regularity.
SIAM J. Math. Anal., August, 2023

2013
Accurately modeling superscalar processor performance with reduced trace.
J. Parallel Distributed Comput., 2013

2012
Design and evaluation of a four-port data cache for high instruction level parallelism reconfigurable processors.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011
An Analytical Performance Model for Co-management of Last-Level Cache and Bandwidth Sharing.
Proceedings of the MASCOTS 2011, 2011

In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order Traces.
Proceedings of the MASCOTS 2011, 2011

2010
Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach.
Softw. Pract. Exp., 2010

2009
An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Accurately approximating superscalar processor performance from traces.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

2008
TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation.
Proceedings of the 2008 International Conference on Parallel Processing, 2008

2007
Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems.
Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007


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