Kishor Kunal

According to our database, Kishor Kunal authored at least 19 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2024

Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance.

Amit Sharma, Teodor-Dumitru Ene, Kishor Kunal, Mingjie Liu, Zafar Hasan, Haoxing Ren

CoRR, 2024

Automated synthesis of mixed-signal ML inference hardware under accuracy constraints.

Kishor Kunal, Jitesh Poojary, S. Ramprasath, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

Reinforcing the Connection between Analog Design and EDA (Invited Paper).

Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching.

Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Ziqing Zeng, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

GNN-Based Hierarchical Annotation for Analog Circuits.

Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

ChipNeMo: Domain-Adapted LLMs for Chip Design.

Mingjie Liu, Teodor-Dumitru Ene, Robert Kirby, Chris Cheng, Nathaniel Ross Pinckney, Rongjian Liang, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Brucek Khailany, Kishor Kunal, Xiaowei Li, Hao Liu, Stuart F. Oberman, Sujeet Omar, Sreedhar Pratty, Jonathan Raiman, Ambar Sarkar, Zhengjiang Shao, Hanfei Sun, Pratik P. Suthar, Varun Tej, Kaizhe Xu, Haoxing Ren

CoRR, 2023

A Multicore GNN Training Accelerator.

Sudipta Mondal, Ramprasath S, Ziqing Zeng, Kishor Kunal, Sachin S. Sapatnekar

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology.

Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S, Kishor Kunal, Sachin S. Sapatnekar, Ramesh Harjani

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

GNNIE: GNN inference engine with load-balancing and graph-specific caching.

Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Sachin S. Sapatnekar

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

ALIGN: A System for Automating Analog Layout.

Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar

IEEE Des. Test, 2021

GNNIE: GNN Inference Engine with Load-balancing and Graph-Specific Caching.

Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Sachin S. Sapatnekar

CoRR, 2021

Machine Learning Techniques in Analog Layout Automation.

Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology.

Vidya A. Chhabria, Kishor Kunal, Masoud Zabihi, Sachin S. Sapatnekar

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models.

Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Learning from Experience: Applying ML to Analog Circuit Design.

Kishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

A general approach for identifying hierarchical symmetry constraints for analog circuit layout.

Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk).

Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits.

Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

ALIGN: Open-Source Analog Layout Automation from the Ground Up.

Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar

Proceedings of the 56th Annual Design Automation Conference 2019, 2019