Kirti Gupta

Orcid: 0000-0003-1691-5208

According to our database1, Kirti Gupta authored at least 32 papers between 2011 and 2024.

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Bibliography

2024
A Monolithic Cybersecurity Architecture for Power Electronic Systems.
IEEE Trans. Smart Grid, July, 2024

Delay-Aware Semantic Sampling in Power Electronic Systems.
IEEE Trans. Smart Grid, July, 2024

Demonstration of denial of charging attack on electric vehicle charging infrastructure and its consequences.
Int. J. Crit. Infrastructure Prot., 2024

Integrating LSTM and NLP techniques for essay generation.
Intell. Decis. Technol., 2024

2023
Memristor-Based Architectures for PFSCL Circuit Realizations.
Circuits Syst. Signal Process., August, 2023

Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell.
Microelectron. J., 2023

Impact Assessment of Data Integrity Attacks in MVDC Shipboard Power Systems.
CoRR, 2023

2022
On improving the performance of dynamic positive-feedback source-coupled logic (D-PFSCL) through inclusion of transmission gates.
Microprocess. Microsystems, April, 2022

A novel read decoupled 8T1M nvSRAM cell for near threshold operation.
Microelectron. J., 2022

Test Suites Generation using UML Modelling and Heuristic Techniques: A Systematic Study.
Proceedings of the 4th International Conference on Information Management & Machine Intelligence, 2022

Handwriting Generation and Synthesis using Recurrent Neural Networks.
Proceedings of the 13th International Conference on Computing Communication and Networking Technologies, 2022

2021
Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm.
Microprocess. Microsystems, September, 2021

A novel PVT-variation-tolerant Schmitt-trigger-based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub-threshold region.
Int. J. Circuit Theory Appl., 2021

A data-independent 9T SRAM cell with enhanced ION/IOFF ratio and RBL voltage swing in near threshold and sub-threshold region.
Int. J. Circuit Theory Appl., 2021

Was the Update of the 2015 Business Review Letter to the IEEE Justified?
IEEE Commun. Stand. Mag., 2021

2020
A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability.
Microelectron. J., 2020

A new realization scheme for dynamic PFSCL style.
Integr., 2020

Model and Design of Improved Current Mode Logic Gates - Differential and Single-ended
Springer, ISBN: 978-981-15-0981-0, 2020

2019
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
Pentavariate V<sub>min</sub> Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

MCML Dynamic Register Design.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017
A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist.
IEEE Trans. Very Large Scale Integr. Syst., 2017

On Improving the Performance of Dynamic DCVSL Circuits.
J. Electr. Comput. Eng., 2017

New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies.
J. Circuits Syst. Comput., 2017

Implementation and Performance Comparison of a Four-Bit Ripple-Carry Adder Using Different MOS Current Mode Logic Topologies.
Proceedings of the Computational Science and Its Applications - ICCSA 2017, 2017

2016
New Proposal for MCML Based Three-Input Logic Implementation.
VLSI Design, 2016

MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells.
Microelectron. J., 2016

A Novel Bulk Drain Connected 6T SRAM Cell.
Proceedings of the Advances in Computing and Data Sciences, 2016

2015
Multi-resolution wavelet-based image fusion for iris recognition.
Int. J. Appl. Pattern Recognit., 2015

2014
An efficient triple-tail cell based PFSCL D latch.
Microelectron. J., 2014

2013
Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells.
Microelectron. J., 2013

2011
New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic.
J. Electr. Comput. Eng., 2011


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