Kiran K. Gunnam

According to our database, Kiran K. Gunnam authored at least 14 papers between 2004 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

An efficient reconfigurable hardware accelerator for convolutional neural networks.

Anaam Ansari, Kiran K. Gunnam, Tokunbo Ogunfunmi

Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2013

Trellis-Based Extended Min-Sum Algorithm for Non-Binary LDPC Codes and its Hardware Structure.

Erbao Li, David Declercq, Kiran K. Gunnam

IEEE Trans. Commun., 2013

Low latency T-EMS decoder for non-binary LDPC codes.

Erbao Li, Francisco Garcia-Herrero, David Declercq, Kiran K. Gunnam, Jesus Omar Lacruz, Javier Valls

Proceedings of the 2013 Asilomar Conference on Signals, 2013

2011

Trellis based Extended Min-Sum for decoding nonbinary LDPC codes.

Erbao Li, Kiran K. Gunnam, David Declercq

Proceedings of the 8th International Symposium on Wireless Communication Systems, 2011

2009

Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels.

Weihuang Wang, Euncheol Kim, Kiran K. Gunnam, Gwan S. Choi

J. Low Power Electron., 2009

Comments on "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes".

Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary

EURASIP J. Embed. Syst., 2009

Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels.

Weihuang Wang, Gwan S. Choi, Kiran K. Gunnam

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008

Next generation iterative LDPC solutions for magnetic recording storage.

Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary, Shaohua Yang, Yuanxing Lee

Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

2007

A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes.

Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard.

Kiran K. Gunnam, Gwan Choi, Weihuang Wang, Mark B. Yeary

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax.

Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary, Mohammed Atiquzzaman

Proceedings of IEEE International Conference on Communications, 2007

2006

Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation.

Kiran K. Gunnam

PhD thesis, 2006

2005

New optimizations for carrier synchronization in single carrier systems.

Kiran K. Gunnam, Kanu Chadha, Mark Yeary

Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

2004

An LDPC decoding schedule for memory access reduction.

Kiran K. Gunnam, Gwan Choi, Mark Yeary

Proceedings of the 2004 IEEE International Conference on Acoustics, 2004