Kiran Bondalapati

According to our database1, Kiran Bondalapati authored at least 10 papers between 1997 and 2002.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2002
Reconfigurable computing systems.
Proc. IEEE, 2002

2001
Parallelizing DSP Nested Loops on Reconfigurable Architectures using Data Context Switching.
Proceedings of the 38th Design Automation Conference, 2001

2000
Dynamic Data Layouts for Cache-Conscious Factorization of DFT.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

Loop Pipelining and Optimization for Run Time Reconfiguration.
Proceedings of the Parallel and Distributed Processing, 2000

1999
Hardware Object Selection for Mapping Loops onto Reconfigurable Architectures.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

DEFACTO: A Design Environment for Adaptive Computing Technology.
Proceedings of the Parallel and Distributed Processing, 1999

DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Dynamic Precision Management for Loop Computations on Reconfigurable Architectures.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998
Mapping Loops onto Reconfigurable Architectures.
Proceedings of the Field-Programmable Logic and Applications, 1998

1997
Multicast on Irregular Switch-Based Networks with Wormhole Routing.
Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997


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