Kimiyoshi Usami
Orcid: 0000-0002-8911-3313
According to our database1,
Kimiyoshi Usami
authored at least 82 papers
between 1989 and 2024.
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Bibliography
2024
Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024
An On-chip Digital Aging Sensor Circuit utilizing Leakage-current based Charge Accumulation.
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
2023
A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023
A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 200mV Operable On-Chip Temperature Sensor for IoT Devices Powered by Energy Harvesters with Ultra-Low Output Voltage.
Proceedings of the IEEE International Conference on Internet of Things and Intelligence Systems, 2023
2022
Optimal switching time to minimize store energy in MTJ-based flip-flops under process and temperature variations.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022
2021
Energy Efficient Approximate Storing of Image Data for MTJ Based Non-Volatile Flip-Flops and MRAM.
IEICE Trans. Electron., 2021
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops.
Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021
2020
Energy Efficient Approximate Storing of Image Data for MTJ Based Non-volatile Memory.
Proceedings of the 9th Non-Volatile Memory Systems and Applications Symposium, 2020
Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization.
Proceedings of the 2020 IEEE Symposium in Low-Power and High-Speed Chips, 2020
2018
A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018
Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application.
Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018
2017
Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Energy-Efficient Standard Cell Memory with Optimized Body-Bias Separation in Silicon-on-Thin-BOX (SOTB).
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI.
Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017
Digital embedded memory scheme using voltage scaling and body bias separation for low-power system.
Proceedings of the International SoC Design Conference, 2017
Proceedings of the International SoC Design Conference, 2017
2016
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications.
IEICE Trans. Electron., 2016
Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems.
IEICE Trans. Electron., 2016
2015
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units.
IEICE Trans. Electron., 2015
A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode.
IEICE Trans. Electron., 2015
An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015
2014
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014
Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014
Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Micro, 2013
Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design.
IEICE Trans. Electron., 2013
Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface.
Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
2012
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012
Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Trade-off analysis of fine-grained power gating methods for functional units in a CPU.
Proceedings of the 2012 IEEE Symposium on Low-Power and High-Speed Chips, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units.
IPSJ Trans. Syst. LSI Des. Methodol., 2011
Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Dynamic V<sub>DD</sub> Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
2010
Proceedings of the NOCS 2010, 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the Architecture of Computing Systems, 2009
2008
Proceedings of the 26th International Conference on Computer Design, 2008
Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2002
J. Circuits Syst. Comput., 2002
Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
2000
Proceedings of the 37th Conference on Design Automation, 2000
Low-power technique for on-chip memory using biased partitioning and access concentration.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
Proceedings of ASP-DAC 2000, 2000
1998
Automated low-power technique exploiting multiple supply voltages applied to a media processor.
IEEE J. Solid State Circuits, 1998
A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme.
IEEE J. Solid State Circuits, 1998
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques.
Proceedings of the 35th Conference on Design Automation, 1998
A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
1995
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995
1990
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990
1989