Kihwan Seong
According to our database1,
Kihwan Seong
authored at least 9 papers
between 2016 and 2024.
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Collaborative distances:
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Bibliography
2024
13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2020
22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table.
IEEE Trans. Biomed. Circuits Syst., 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
8.7 A 0.0047mm<sup>2</sup> highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016