Kia Bazargan

According to our database, Kia Bazargan authored at least 95 papers between 1998 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

SimBU: Self-Similarity-Based Hybrid Binary-Unary Computing for Nonlinear Functions.

Alireza Khataei, Gaurav Singh, Kia Bazargan

IEEE Trans. Computers, September, 2024

CompressedLUT: An Open Source Tool for Lossless Compression of Lookup Tables for Function Evaluation and Beyond.

Alireza Khataei, Kia Bazargan

Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

2023

Constant Coefficient Multipliers Using Self-Similarity-Based Hybrid Binary-Unary Computing.

Alireza Khataei, Kia Bazargan

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Approximate Hybrid Binary-Unary Computing with Applications in BERT Language Model and Image Processing.

Alireza Khataei, Gaurav Singh, Kia Bazargan

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Optimizing Hybrid Binary-Unary Hardware Accelerators Using Self-Similarity Measures.

Alireza Khataei, Gaurav Singh, Kia Bazargan

Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022

Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs.

S. Rasoul Faraji, Pierre Abillama, Kia Bazargan

ACM Trans. Reconfigurable Technol. Syst., 2022

2020

Deterministic Shuffling Networks to Implement Stochastic Circuits in Parallel.

Zhiheng Wang, Devan Larso, Morgen Barker, Soheil Mohajer, Kia Bazargan

IEEE Trans. Very Large Scale Integr. Syst., 2020

Parallel Unary Computing Based on Function Derivatives.

Soheil Mohajer, Zhiheng Wang, Kia Bazargan, Yuyang Li

ACM Trans. Reconfigurable Technol. Syst., 2020

Hybrid Binary-Unary Hardware Accelerator.

S. Rasoul Faraji, Kia Bazargan

IEEE Trans. Computers, 2020

Energy-Efficient Pulse-Based Convolution for Near-Sensor Processing.

M. Hassan Najafi, S. Rasoul Faraji, Kia Bazargan, David J. Lilja

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

HBUCNNA: Hybrid Binary-Unary Convolutional Neural Network Accelerator.

S. Rasoul Faraji, Pierre Abillama, Gaurav Singh, Kia Bazargan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Hybrid Binary-Unary Truncated Multiplication for DSP Applications on FPGAs.

S. Rasoul Faraji, Kia Bazargan

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Low-Cost Approximate Constant Coefficient Hybrid Binary-Unary Multiplier for DSP Applications.

S. Rasoul Faraji, Pierre Abillama, Kia Bazargan

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019

Accelerating Deterministic Bit-Stream Computing with Resolution Splitting.

M. Hassan Najafi, S. Rasoul Faraji, Bingzhe Li, David J. Lilja, Kia Bazargan

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

HBUNN - Hybrid Binary-Unary Neural Network: Realizing a Complete CNN on an FPGA.

Sayed Abdolrasouol Faraji, Gaurav Singh, Kia Bazargan

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream Processing.

S. Rasoul Faraji, M. Hassan Najafi, Bingzhe Li, David J. Lilja, Kia Bazargan

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Energy-Efficient Near-Sensor Convolution using Pulsed Unary Processing.

M. Hassan Najafi, S. Rasoul Faraji, Kia Bazargan, David J. Lilja

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018

Low-Cost Sorting Network Circuits Using Unary Processing.

M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan

IEEE Trans. Very Large Scale Integr. Syst., 2018

Routing Magic: Performing Computations Using Routing Networks and Voting Logic on Unary Encoded Data.

Soheil Mohajer, Zhiheng Wang, Kia Bazargan

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Low latency parallel implementation of traditionally-called stochastic circuits using deterministic shuffling networks.

Zhiheng Wang, Soheil Mohajer, Kia Bazargan

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map.

Zhiheng Wang, Ryan N. Goh, Kia Bazargan, Arnd Scheel, Naman Saraf

IEEE Trans. Very Large Scale Integr. Syst., 2017

Time-Encoded Values for Highly Efficient Stochastic Circuits.

M. Hassan Najafi, Shiva Jamali-Zavareh, David J. Lilja, Marc D. Riedel, Kia Bazargan, Ramesh Harjani

IEEE Trans. Very Large Scale Integr. Syst., 2017

Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits.

M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan

IEEE Trans. Computers, 2017

An Overview of Time-Based Computing with Stochastic Constructs.

M. Hassan Najafi, Shiva Jamali-Zavareh, David J. Lilja, Marc D. Riedel, Kia Bazargan, Ramesh Harjani

IEEE Micro, 2017

A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing.

M. Hassan Najafi, Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel

ACM J. Emerg. Technol. Comput. Syst., 2017

A memory optimized mersenne-twister random number generator.

Naman Saraf, Kia Bazargan

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Power and Area Efficient Sorting Networks Using Unary Processing.

M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016

Polynomial Arithmetic Using Sequential Stochastic Logic.

Naman Saraf, Kia Bazargan

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

t-QuadPlace: Timing Driven Quadratic Placement using Quadrisection Partitioning for FPGAs (Abstact Only).

Nimish Agashiwala, Satya Prakash Upadhyay, Kia Bazargan

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Polysynchronous stochastic circuits.

M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Axilog: Abstractions for Approximate Hardware Design and Reuse.

Divya Mahajan, Kartik Ramkrishnan, Rudra Jariwala, Amir Yazdanbakhsh, Jongse Park, Bradley Thwaites, Anandhavel Nagendrakumar, Abbas Rahimi, Hadi Esmaeilzadeh, Kia Bazargan

IEEE Micro, 2015

Axilog: language support for approximate hardware design.

Amir Yazdanbakhsh, Divya Mahajan, Bradley Thwaites, Jongse Park, Anandhavel Nagendrakumar, Sindhuja Sethuraman, Kartik Ramkrishnan, Nishanthi Ravindran, Rudra Jariwala, Abbas Rahimi, Hadi Esmaeilzadeh, Kia Bazargan

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Randomness meets feedback: stochastic implementation of logistic map dynamical system.

Zhiheng Wang, Naman Saraf, Kia Bazargan, Arnd Scheel

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Computation on Stochastic Bit Streams Digital Image Processing Case Studies.

Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel

IEEE Trans. Very Large Scale Integr. Syst., 2014

Logical Computation on Stochastic Bit Streams with Linear Finite-State Machines.

Peng Li, David J. Lilja, Weikang Qian, Marc D. Riedel, Kia Bazargan

IEEE Trans. Computers, 2014

Binary stochastic implementation of digital logic.

Yanzi Zhu, Peiran Suo, Kia Bazargan

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

IIR filters using stochastic arithmetic.

Naman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Stochastic functions using sequential logic.

Naman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Sequential logic to transform probabilities.

Naman Saraf, Kia Bazargan

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012

Case Studies of Logical Computation on Stochastic Bit Streams.

Peng Li, Weikang Qian, David J. Lilja, Kia Bazargan, Marc D. Riedel

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

An efficient implementation of numerical integration using logical computation on stochastic bit streams.

Weikang Qian, Chen Wang, Peng Li, David J. Lilja, Kia Bazargan, Marc D. Riedel

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic.

Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

The synthesis of linear Finite State Machine-based Stochastic Computational Elements.

Peng Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

An Architecture for Fault-Tolerant Computation with Stochastic Logic.

Weikang Qian, Xin Li, Marc D. Riedel, Kia Bazargan, David J. Lilja

IEEE Trans. Computers, 2011

FPGA placement by graph isomorphism (abstract only).

Hossein Omidian Savarbaghi, Kia Bazargan

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010

Improvements on Efficiency and Efficacy of SPFD-Based Rewiring for LUT-Based Circuits.

Pongstorn Maidee, Kia Bazargan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A fast SPFD-based rewiring technique.

Pongstorn Maidee, Kia Bazargan

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Fast and Accurate Statistical Criticality Computation Under Process Variations.

Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Estimation and optimization of reliability of noisy digital circuits.

Satish Sivaswamy, Kia Bazargan, Marc D. Riedel

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

The synthesis of combinational logic to generate probabilities.

Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A reconfigurable stochastic architecture for highly reliable computing.

Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Using randomization to cope with circuit uncertainty.

Hamid Safizadeh, Mohammad Tahghighi, Ehsan K. Ardestani, Gholamhossein Tavasoli, Kia Bazargan

Proceedings of the Design, Automation and Test in Europe, 2009

A tileable switch module architecture for homogeneous 3D FPGAs.

Seyyed Ahmad Razavi, Morteza Saheb Zamani, Kia Bazargan

Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008

Physical Design for Three-Dimensional Circuits.

Kia Bazargan, Sachin S. Sapatnekar

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

FPGA Technology Mapping, Placement, and Routing.

Kia Bazargan

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs.

Satish Sivaswamy, Kia Bazargan

ACM Trans. Reconfigurable Technol. Syst., 2008

Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction.

Hushrav Mogal, Kia Bazargan

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

FPGA family composition and effects of specialized blocks.

Pongstorn Maidee, Nagib Hakim, Kia Bazargan

Proceedings of the FPL 2008, 2008

2007

Guest Editorial.

Kia Bazargan, André DeHon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Clustering based pruning for statistical criticality computation under process variations.

Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs.

Satish Sivaswamy, Kia Bazargan

Proceedings of the FPL 2007, 2007

A generalized and unified SPFD-based rewiring technique.

Pongstorn Maidee, Kia Bazargan

Proceedings of the FPL 2007, 2007

Variation-aware routing for FPGAs.

Satish Sivaswamy, Kia Bazargan

Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

Microarchitecture floorplanning for sub-threshold leakage reduction.

Hushrav Mogal, Kia Bazargan

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Statistical Analysis and Design of HARP FPGAs.

Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Three-dimensional place and route for FPGAs.

Cristinel Ababei, Hushrav Mogal, Kia Bazargan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Non-contiguous linear placement for reconfigurable fabrics.

Cristinel Ababei, Kia Bazargan

Int. J. Embed. Syst., 2006

Defect-Tolerant FPGA Architecture Exploration.

Pongstorn Maidee, Kia Bazargan

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005

Timing-driven partitioning-based placement for island style FPGAs.

Pongstorn Maidee, Cristinel Ababei, Kia Bazargan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory.

Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan

J. Comput. Sci. Technol., 2005

Placement and Routing in 3D Integrated Circuits.

Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar

IEEE Des. Test Comput., 2005

HARP: hard-wired routing pattern FPGAs.

Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

3D FPGAs: placement, routing, and architecture evaluation (abstract only).

Cristinel Ababei, Hushrav Mogal, Kia Bazargan

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004

Editorial: Special issue on dynamically adaptable embedded systems.

John C. Lach, Kia Bazargan

ACM Trans. Embed. Comput. Syst., 2004

Exploring Potential Benefits of 3D FPGA Integration.

Cristinel Ababei, Pongstorn Maidee, Kia Bazargan

Proceedings of the Field Programmable Logic and Application, 2004

Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory.

Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan

Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004

2003

Timing Minimization by Statistical Timing hMetis-based Partitioning.

Cristinel Ababei, Kia Bazargan

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Incremental Placement for Timing Optimization.

Wonjoon Choi, Kia Bazargan

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Placement Method Targeting Predictability Robustness and Performance.

Cristinel Ababei, Kia Bazargan

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Linear Placement for Static / Dynamic Reconfiguration in JBits.

Vamsi Krishna Marreddy, Sharareh Noorbaloochi, Kia Bazargan

Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming.

Karthikeyan Bhasyam, Kia Bazargan

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration.

Wonjoon Choi, Kia Bazargan

Proceedings of the 2003 Design, 2003

Fast timing-driven partitioning-based placement for island style FPGAs.

Pongstorn Maidee, Cristinel Ababei, Kia Bazargan

Proceedings of the 40th Design Automation Conference, 2003

2002

Multi-objective circuit partitioning for cutsize and path-based delay minimization.

Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Statistical Timing Driven Partitioning for VLSI Circuits.

Cristinel Ababei, Kia Bazargan

Proceedings of the 2002 Design, 2002

A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator.

Jinghuan Chen, Jaekyun Moon, Kia Bazargan

Proceedings of the 39th Design Automation Conference, 2002

2001

Fast floorplanning for effective prediction and construction.

Abhishek Ranjan, Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh

IEEE Trans. Very Large Scale Integr. Syst., 2001

Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures.

Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh

Proceedings of the 38th Design Automation Conference, 2001

2000

Fast Template Placement for Reconfigurable Computing Systems.

Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh

IEEE Des. Test Comput., 2000

3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems.

Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh

Des. Autom. Embed. Syst., 2000

Fast Hierarchical Floorplanning with Congestion and Timing Control.

Abhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Fast and accurate estimation of floorplans in logic/high-level synthesis.

Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

A C to Hardware/Software Compiler.

Kia Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh

Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999

Nostradamus: a floorplanner of uncertain designs.

Kia Bazargan, Samjung Kim, Majid Sarrafzadeh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998

Nostradamus: a floorplanner of uncertain design.

Kia Bazargan, Samjung Kim, Majid Sarrafzadeh

Proceedings of the 1998 International Symposium on Physical Design, 1998