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We stand with Ukraine

Ki-Seok Chung

Orcid: 0000-0002-2908-8443

According to our database¹, Ki-Seok Chung authored at least 83 papers between 1994 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2023

DiffusionVID: Denoising Object Boxes With Spatio-Temporal Conditioning for Video Object Detection.

[BibT_eX]

[DOI]

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IEEE Access, 2023

iNLC: Iterative Noisy Label Correction.

[BibT_eX]

[DOI]

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Proceedings of the 17th International Conference on Signal-Image Technology & Internet-Based Systems, 2023

Alert Refresh System for Mitigating RowHammer.

[BibT_eX]

[DOI]

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Proceedings of the 20th International SoC Design Conference, 2023

Dynamic Partitioning Method for Near-Memory Parallel Processing of Sparse Matrix-Vector Multiplication.

[BibT_eX]

[DOI]

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Proceedings of the 49th Annual Conference of the IEEE Industrial Electronics Society, 2023

Token Merging with Class Importance Score.

[BibT_eX]

[DOI]

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Proceedings of the 49th Annual Conference of the IEEE Industrial Electronics Society, 2023

An Efficient Noisy Label Learning Method with Semi-supervised Learning: An Efficient Noisy Label Learning Method with Semi-supervised Learning.

[BibT_eX]

[DOI]

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Proceedings of the 2023 6th International Conference on Machine Vision and Applications, 2023

2022

Regularized Convolutional Neural Network for Highly Effective Parallel Processing.

[BibT_eX]

[DOI]

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J. Comput. Sci. Eng., 2022

DAFA: Diversity-Aware Feature Aggregation for Attention-Based Video Object Detection.

[BibT_eX]

[DOI]

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IEEE Access, 2022

What Matters for Out-of-Distribution Detectors using Pre-trained CNN?

[BibT_eX]

[DOI]

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Proceedings of the 17th International Joint Conference on Computer Vision, 2022

2021

Selection-based Low-cost Check Node Operation for Extended Min-Sum Algorithm.

[BibT_eX]

[DOI]

Kyeong-Bin Park

,

KSII Trans. Internet Inf. Syst., 2021

Iterative Pseudo-Soft-Reliability-Based Majority-Logic Decoding for NAND Flash Memory.

[BibT_eX]

[DOI]

Kyeong-Bin Park

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IEEE Access, 2021

CLC: Noisy Label Correction via Curriculum Learning.

[BibT_eX]

[DOI]

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Proceedings of the IEEE Symposium Series on Computational Intelligence, 2021

Robustness-Aware Filter Pruning for Robust Neural Networks Against Adversarial Attacks.

[BibT_eX]

[DOI]

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Proceedings of the 2021 IEEE 31st International Workshop on Machine Learning for Signal Processing (MLSP), 2021

EdgeRL: A Light-Weight C/C++ Framework for On-Device Reinforcement Learning.

[BibT_eX]

[DOI]

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Proceedings of the 18th International SoC Design Conference, 2021

Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology.

[BibT_eX]

[DOI]

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Kyungjoon Chang

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Proceedings of the 18th International SoC Design Conference, 2021

Reducing Refresh Overhead with In-DRAM Error Correction Codes.

[BibT_eX]

[DOI]

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Proceedings of the 18th International SoC Design Conference, 2021

HammerFilter: Robust Protection and Low Hardware Overhead Method for RowHammer.

[BibT_eX]

[DOI]

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Proceedings of the 39th IEEE International Conference on Computer Design, 2021

FlowNetU: Accurate Uncertainty Estimation of Optical Flow for Video Object Detection.

[BibT_eX]

[DOI]

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Proceedings of the AIPR 2021: 4th International Conference on Artificial Intelligence and Pattern Recognition, Xiamen, China, September 24, 2021

2020

Direct Conversion: Accelerating Convolutional Neural Networks Utilizing Sparse Input Activation.

[BibT_eX]

[DOI]

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Proceedings of the 46th Annual Conference of the IEEE Industrial Electronics Society, 2020

A Confidence-Calibrated MOBA Game Winner Predictor.

[BibT_eX]

[DOI]

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Proceedings of the IEEE Conference on Games, 2020

2019

GRAM: Gradient Rescaling Attention Model for Data Uncertainty Estimation in Single Image Super Resolution.

[BibT_eX]

[DOI]

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Proceedings of the 18th IEEE International Conference On Machine Learning And Applications, 2019

2018

Runtime Memory Controller Profiling with Performance Analysis for DRAM Memory Controllers.

[BibT_eX]

[DOI]

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J. Circuits Syst. Comput., 2018

HMC-MAC: Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube.

[BibT_eX]

[DOI]

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Kyeong-Bin Park

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IEEE Comput. Archit. Lett., 2018

Multi-way interactive capacitive touch system with palm rejection of active stylus for 86" touch screen panels.

[BibT_eX]

[DOI]

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Kyeong-Bin Park

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Kwang-Hyun Baek

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Seong-Kwan Hong

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Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Image Blending Techniques Based on GPU Acceleration.

[BibT_eX]

[DOI]

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Proceedings of the 2018 International Conference on Image and Graphics Processing, 2018

Implementation of a CNN accelerator on an Embedded SoC Platform using SDSoC.

[BibT_eX]

[DOI]

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Kyeong-Bin Park

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Proceedings of the 2nd International Conference on Digital Signal Processing, 2018

Per-bank refresh with adaptive early termination for high density DRAM.

[BibT_eX]

[DOI]

Hyun-Woong Yang

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Proceedings of the 4th International Conference on Communication and Information Processing, 2018

Log-quantization on GRU networks.

[BibT_eX]

[DOI]

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Proceedings of the 4th International Conference on Communication and Information Processing, 2018

Efficient SIMD implementation for accelerating convolutional neural network.

[BibT_eX]

[DOI]

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Proceedings of the 4th International Conference on Communication and Information Processing, 2018

Optimization of FPGA-based LDPC decoder using high-level synthesis.

[BibT_eX]

[DOI]

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Kyeong-Bin Park

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Proceedings of the 4th International Conference on Communication and Information Processing, 2018

2017

Self-Adaptive Termination Check of Min-Sum Algorithm for LDPC Decoders Using the First Two Minima.

[BibT_eX]

[DOI]

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KSII Trans. Internet Inf. Syst., 2017

CasHMC: A Cycle-Accurate Simulator for Hybrid Memory Cube.

[BibT_eX]

[DOI]

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IEEE Comput. Archit. Lett., 2017

Modified Convolution Neural Network for Highly Effective Parallel Processing.

[BibT_eX]

[DOI]

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Proceedings of the 2017 IEEE International Conference on Information Reuse and Integration, 2017

2016

User-Centric Power Management for Embedded CPUs Using CPU Bandwidth Control.

[BibT_eX]

[DOI]

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IEEE Trans. Mob. Comput., 2016

Parallel LDPC Decoding on a Heterogeneous Platform using OpenCL.

[BibT_eX]

[DOI]

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KSII Trans. Internet Inf. Syst., 2016

Self-Adaptive Scaled Min-Sum Algorithm for LDPC Decoders Based on Delta-Min.

[BibT_eX]

[DOI]

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IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

2015

Conditional termination check min-sum algorithm for efficient LDPC decoders.

[BibT_eX]

[DOI]

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IEICE Electron. Express, 2015

Quality of Service-Aware Dynamic Voltage and Frequency Scaling for Embedded GPUs.

[BibT_eX]

[DOI]

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IEEE Comput. Archit. Lett., 2015

Analysis of various DRAM devices from power consumption's perspective.

[BibT_eX]

[DOI]

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Proceedings of the 10th IEEE International Conference on Networking, 2015

Parallel LDPC decoding on a GPU using OpenCL and global memory for accelerators.

[BibT_eX]

[DOI]

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Proceedings of the 10th IEEE International Conference on Networking, 2015

2014

Design of OpenCL framework for embedded multi-core processors.

[BibT_eX]

[DOI]

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IEEE Trans. Consumer Electron., 2014

2013

Dynamic Power Management Technique for Multicore Based Embedded Mobile Devices.

[BibT_eX]

[DOI]

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IEEE Trans. Ind. Informatics, 2013

A Parallelization Technique with Integrated Multi-Threading for Video Decoding on Multi-core Systems.

[BibT_eX]

[DOI]

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KSII Trans. Internet Inf. Syst., 2013

Dynamic voltage and frequency scaling scheme for an adaptive LDPC decoder using SNR estimation.

[BibT_eX]

[DOI]

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EURASIP J. Wirel. Commun. Netw., 2013

Novel level-up shifters for high performance and low power mobile devices.

[BibT_eX]

[DOI]

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Proceedings of the IEEE International Conference on Consumer Electronics, 2013

2012

Ultra low power and high speed FPGA design with CNFET.

[BibT_eX]

[DOI]

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Proceedings of the International Symposium on Communications and Information Technologies, 2012

2011

Overlapped message passing technique with resource sharing for high speed CMMB LDPC decoder.

[BibT_eX]

[DOI]

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IEEE Trans. Consumer Electron., 2011

Multi-threaded syntax element partitioning for parallel entropy decoding.

[BibT_eX]

[DOI]

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IEEE Trans. Consumer Electron., 2011

A Technique for Fast Process Creation Based on Creation Location.

[BibT_eX]

[DOI]

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J. Comput. Sci. Eng., 2011

Parallel LDPC decoding using CUDA and OpenMP.

[BibT_eX]

[DOI]

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EURASIP J. Wirel. Commun. Netw., 2011

An adaptive low-power LDPC decoder using SNR estimation.

[BibT_eX]

[DOI]

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EURASIP J. Wirel. Commun. Netw., 2011

A Test Method for Power Management of SoC-based Microprocessors.

[BibT_eX]

[DOI]

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Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011

FPGA implementation of unified kernel structure for MDCT/IMDCT in audio coding schemes.

[BibT_eX]

[DOI]

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Proceedings of the International SoC Design Conference, 2011

LDPC decoding for CMMB utilizing OpenMP and CUDA parallelization.

[BibT_eX]

[DOI]

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Proceedings of the IEEE 17th Asia-Pacific Conference on Communications, 2011

2010

Stage-based frame-partitioned parallelization of H.264/AVC decoding.

[BibT_eX]

[DOI]

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IEEE Trans. Consumer Electron., 2010

A predictive dynamic power management technique for embedded mobile devices.

[BibT_eX]

[DOI]

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IEEE Trans. Consumer Electron., 2010

2009

Thermal sensor allocation and placement for reconfigurable systems.

[BibT_eX]

[DOI]

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ACM Trans. Design Autom. Electr. Syst., 2009

Memory efficient multi-rate regular LDPC decoder for CMMB.

[BibT_eX]

[DOI]

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IEEE Trans. Consumer Electron., 2009

Thermal-Aware High-Level Synthesis Based on Network Flow Method.

[BibT_eX]

[DOI]

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J. Circuits Syst. Comput., 2009

A novel SoC platform based multi-IP verification and performance measurement.

[BibT_eX]

[DOI]

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Int. J. Inf. Commun. Technol., 2009

Optimisation of RunBefore decoder and first one detector for MPEG-4 AVC/H.264 CAVLC decoding.

[BibT_eX]

[DOI]

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Int. J. Inf. Commun. Technol., 2009

Low Power MAC Design with Variable Precision Support.

[BibT_eX]

[DOI]

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IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Implementation of IEEE802.11a software defined receiver on chip multi-processor architecture using OpenMP.

[BibT_eX]

[DOI]

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Proceedings of the 2009 International Conference on Hybrid Information Technology, 2009

Performance evaluation of on-chip interconnect IP using CBR traffic generator model.

[BibT_eX]

[DOI]

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Proceedings of the 2009 International Conference on Hybrid Information Technology, 2009

2008

A unified power measurement and management platform for pipelined MPSoC executions.

[BibT_eX]

[DOI]

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Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Predictive power aware management for embedded mobile devices.

[BibT_eX]

[DOI]

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Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Timing driven force-directed floorplanning with incremental static timing analyzer.

[BibT_eX]

[DOI]

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Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

An incremental floorplanning algorithm for temperature reduction.

[BibT_eX]

[DOI]

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Proceedings of the 2007 IEEE International SOC Conference, 2007

Design of Low Power MAC Operator with Dual Precision Mode.

[BibT_eX]

[DOI]

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Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007

2004

Profile-based optimal intra-task voltage scheduling for hard real-time applications.

[BibT_eX]

[DOI]

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Proceedings of the 41th Design Automation Conference, 2004

2003

Properties of A1/BaTa2O6/GaN MIS Structure.

[BibT_eX]

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Proceedings of the International Conference on VLSI, 2003

2002

Synthesis and Optimization of Combinational Interface Circuits.

[BibT_eX]

[DOI]

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Rajesh K. Gupta

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J. VLSI Signal Process., 2002

A Complete Model for Glitch Analysis in Logic Circuits.

[BibT_eX]

[DOI]

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J. Circuits Syst. Comput., 2002

Enhanced bus invert encodings for low-power.

[BibT_eX]

[DOI]

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Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

G-vector: A New Model for Glitch Analysis in Logic Circuits.

[BibT_eX]

[DOI]

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J. VLSI Signal Process., 2001

A Static Estimation Technique of Power Sensitivity in Logic Circuits.

[BibT_eX]

[DOI]

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Chien-Liang Liu

Proceedings of the 38th Design Automation Conference, 2001

2000

Decomposition of Bus-Invert Coding for Low-Power I/O.

[BibT_eX]

[DOI]

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J. Circuits Syst. Comput., 2000

Behavioral-level partitioning for low power design in control-dominated application.

[BibT_eX]

[DOI]

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Chien-Liang Liu

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1998

Modeling and Synthesis of Combinational Logic Circuits: A Power Dissipation Perspective

[BibT_eX]

[DOI]

PhD thesis, 1998

Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction.

[BibT_eX]

[DOI]

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Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

1997

Low power multiplexer decomposition.

[BibT_eX]

[DOI]

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Chien-Liang Liu

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

1996

An algorithm for synthesis of system-level interface circuits.

[BibT_eX]

[DOI]

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Rajesh K. Gupta

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Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1994

A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability.

[BibT_eX]

[DOI]

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Chien-Liang Liu

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

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