Ki Chul Chun
Orcid: 0000-0001-5187-0514
According to our database1,
Ki Chul Chun
authored at least 17 papers
between 2009 and 2021.
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Bibliography
2021
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme.
IEEE J. Solid State Circuits, 2021
IEEE Access, 2021
2020
22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2018
A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2014
A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications.
IEEE J. Solid State Circuits, 2014
2013
A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme.
IEEE J. Solid State Circuits, 2013
A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory.
IEEE J. Solid State Circuits, 2013
A bit-by-bit re-writable Eflash in a generic logic process for moderate-density embedded non-volatile memory applications.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches.
IEEE J. Solid State Circuits, 2012
A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor.
IEEE J. Solid State Circuits, 2012
A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme.
Proceedings of the Symposium on VLSI Circuits, 2012
2011
A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches.
IEEE J. Solid State Circuits, 2011
A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009