Khushbu Chandrakar

According to our database, Khushbu Chandrakar authored at least 3 papers between 2013 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A SAT-Based Methodology for Effective Clock Gating for Power Minimization.

Khushbu Chandrakar, Suchismita Roy

J. Circuits Syst. Comput., 2019

2018

Power Optimization Techniques for High-Level Designs Using Multiple Voltage Components for Low Power Consumption.

Khushbu Chandrakar, Sudeshna Kundu, Suchismita Roy

J. Low Power Electron., 2018

2013

SAT based low power binding to reduce switching activity.

Khushbu Chandrakar, Suchismita Roy

Proceedings of the Sixth International Conference on Contemporary Computing, 2013