Khosrow Hajsadeghi

According to our database, Khosrow Hajsadeghi authored at least 19 papers between 2008 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A Novel Design of 16-bit Multi-Mode 4-Channel Time-Interleaved Delta-Sigma Digital-to-Analog Converter.

Abolfazl Roshanpanah, Pooya Torkzadeh, Khosrow Hajsadeghi, Massoud Dousti

J. Circuits Syst. Comput., September, 2024

2020

Predicting scientific research trends based on link prediction in keyword networks.

Saman Behrouzi, Zahra Shafaeipour Sarmoor, Khosrow Hajsadeghi, Kaveh Kavousi

J. Informetrics, 2020

2019

A 5.3-ps, 8-b Time to Digital Converter Using a New Gain-Reconfigurable Time Amplifier.

Hasan Molaei, Khosrow Hajsadeghi

IEEE Trans. Circuits Syst. II Express Briefs, 2019

2018

Design of low power comparator-reduced hybrid ADC.

Hasan Molaei, Khosrow Hajsadeghi, Ata Khorami

Microelectron. J., 2018

2017

A 1.6 ps 7 b time to digital converter in 0.18 µm CMOS technology.

Hasan Molaei, Khosrow Hajsadeghi

Microelectron. J., 2017

A low-power comparator-reduced flash ADC using dynamic comparators.

Hasan Molaei, Khosrow Hajsadeghi

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Circuit design to improve security of telecommunication devices.

Hengameh Bahrami, Khosrow Hajsadeghi

Proceedings of the IEEE 7th Annual Computing and Communication Workshop and Conference, 2017

2016

A low power high resolution time to digital converter for ADPLL application.

Hasan Molaei, Khosrow Hajsadeghi

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

A wide dynamic range low power 2× time amplifier using current subtraction scheme.

Hasan Molaei, Ata Khorami, Khosrow Hajsadeghi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

A four bit low power 165MS/s flash-SAR ADC for sigma-delta ADC application.

Hasan Molaei, Ata Khorami, Mohammad S. Eslampanah Sendi, Khosrow Hajsadeghi

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014

Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell.

Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow Hajsadeghi

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A Subthreshold Symmetric SRAM Cell With High Read Stability.

Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow Hajsadeghi

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Fine logarithmic adaptive soft morphological algorithm for synthetic aperture radar image segmentation.

Mohaddeseh Koosha, Khosrow Hajsadeghi, Mohammad Koosha

IET Image Process., 2014

12 bits, 40MS/s, low power pipelined SAR ADC.

Vahid Khojasteh Lazarjan, Khosrow Hajsadeghi

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013

A 32kb 90nm 9T-cell sub-threshold SRAM with improved read and write SNM.

Milad Zamani, Sina Hassanzadeh, Khosrow Hajsadeghi, Roghayeh Saeidi

Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

A novel low power 8T-cell sub-threshold SRAM with improved read-SNM.

Sina Hassanzadeh, Milad Zamani, Khosrow Hajsadeghi, Roghayeh Saeidi

Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

2012

New Operational Transconductance Amplifiers using current boosting.

Mehdi Noormohammadi, Vahid Khojasteh Lazarjan, Khosrow Hajsadeghi

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2011

A subthreshold dynamic read SRAM (DRSRAM) based on dynamic stability criteria.

Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow Hajsadeghi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2008

A clock boosting scheme for low voltage circuits.

Amirehsan Behradfar, Saeed Zeinolabedinzadeh, Khosrow Hajsadeghi

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008