Khoa Minh Nguyen

Orcid: 0000-0002-7638-6654

According to our database1, Khoa Minh Nguyen authored at least 7 papers between 2010 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017
13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2016
19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2013
A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver.
IEEE J. Solid State Circuits, 2013

2011
Key receiver circuits for digital beamforming in MMW imaging.
PhD thesis, 2011

2010
Digital phase tightening for millimeter-wave imaging.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010


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