Khawar Sarfraz
Orcid: 0000-0002-2031-4635
According to our database1,
Khawar Sarfraz
authored at least 10 papers
between 2011 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
An Efficient 6TP SRAM-Based CIM Macro With Column ADCs for Binarized Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024
2021
8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE J. Solid State Circuits, 2017
2016
A compact low-power 4-port register file with grounded write bitlines and single-ended read operations.
Integr., 2016
A voltage-scalable zero-delay-overhead scheme for standby power reduction in dynamic register files.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
2015
A 65nm 3.2GHz 44.2mW Low-Vt register file with robust low-capacitance dynamic local bitlines.
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2013
Characterization of a low leakage current and high-speed 7T SRAM circuit with wide voltage margins.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011