Kexin Yang

Orcid: 0000-0002-3630-1003

Affiliations:
  • Synopsys Inc., Mountain View, CA, USA
  • Georgia Institute of Technology, Atlanta, GA, USA (PhD 2018)


According to our database1, Kexin Yang authored at least 15 papers between 2017 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2022
CacheEM: For Reliability Analysis on Cache Memory Aging Due to Electromigration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2021

2020
SRAM Stability Analysis and Performance-Reliability Tradeoff for Different Cache Configurations.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Optimal Accelerated Test Framework for Time-Dependent Dielectric Breakdown Lifetime Parameter Estimation.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Inverse Design of FinFET SRAM Cells.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
Impact of Front-End Wearout Mechanisms on the Performance of a Ring Oscillator-Based Thermal Sensor.
Proceedings of the IEEE 8th International Workshop on Advances in Sensors and Interfaces, 2019

Machine Learning for Detection of Competing Wearout Mechanisms.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Identification of Failure Modes for Circuit Samples with Confounded Causes of Failure.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Reliability and Accelerated Testing of 14nm FinFET Ring Oscillators.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2018
A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technology.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout Mechanisms.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
Analysis of time-dependent dielectric breakdown induced aging of SRAM cache with different configurations.
Microelectron. Reliab., 2017

Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits.
Microelectron. Reliab., 2017


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