Kewal K. Saluja

Erik Larsson

Proceedings of the Design, Automation and Test in Europe, 2010

Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations.

[BibT_eX]

[DOI]

Lin Xie

Azadeh Davoodi

Proceedings of the 47th Design Automation Conference, 2010

Controlling Peak Power Consumption for Scan Based Multiple Weighted Random BIST.

[BibT_eX]

[DOI]

Hiroshi Yokoyama

Hideo Tamamoto

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Modeling Detection Latency with Collaborative Mobile Sensing Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2009

An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2009

An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation.

[BibT_eX]

[DOI]

Inf. Media Technol., 2009

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Low-Area Wrapper Cell Design for Hierarchical SoC Testing.

[BibT_eX]

[DOI]

J. Electron. Test., 2009

False Path Aware Timing Yield Estimation under Variability.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements.

[BibT_eX]

[DOI]

Chunhua Yao

Abhishek A. Sinkar

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Blindly Calibrating Mobile Sensors Using Piecewise Linear Functions.

[BibT_eX]

[DOI]

Chao Wang

Parmesh Ramanathan

Proceedings of the Sixth Annual IEEE Communications Society Conference on Sensor, 2009

Power and thermal constrained test scheduling.

[BibT_eX]

[DOI]

Chunhua Yao

Proceedings of the 2009 IEEE International Test Conference, 2009

DX-compactor: distributed X-compaction for SoCs.

[BibT_eX]

[DOI]

Reshma C. Jumani

Niraj Bharatkumar Jain

Virendra Singh

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies.

[BibT_eX]

[DOI]

Chunhua Yao

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Analysis and test procedures for NOR flash memory defects.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2008

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2008

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

NBTI Degradation: A Problem or a Scare?

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Testing Flash Memories for Tunnel Oxide Defects.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Calibrating Nonlinear Mobile Sensors.

[BibT_eX]

[DOI]

Chao Wang

Parmesh Ramanathan

Parthasarathy Ranganathan

Proceedings of the Fifth Annual IEEE Communications Society Conference on Sensor, 2008

Implementing high availability memory with a duplication cache.

[BibT_eX]

[DOI]

Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Moments Based Blind Calibration in Mobile Sensor Networks.

[BibT_eX]

[DOI]

Chao Wang

Proceedings of IEEE International Conference on Communications, 2008

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing.

[BibT_eX]

[DOI]

Proceedings of the 13th European Test Symposium, 2008

An accurate flip-flop selection technique for reducing logic SER.

[BibT_eX]

[DOI]

Eric L. Hill

Mikko H. Lipasti

Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

A Novel ATPG Method for Capture Power Reduction during Scan Testing.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2007

Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2007

On NBTI Degradation Process in Digital Logic Circuits.

[BibT_eX]

[DOI]

Xiangning Yang

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Combating NBTI Degradation via Gate Sizing.

[BibT_eX]

[DOI]

Xiangning Yang

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

2006

Instruction-Based Self-Testing of Delay Faults in Pipelined Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Energy Estimation of the Memory Subsystem in Multiprocessor Systems.

[BibT_eX]

[DOI]

Mikko H. Lipasti

J. Low Power Electron., 2006

Vulnerability of Surveillance Networks to Faults.

[BibT_eX]

[DOI]

Int. J. Distributed Sens. Networks, 2006

A New Method for Low-Capture-Power Test Generation for Scan Testing.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2006

A Per-Test Fault Diagnosis Method Based on the <i>X</i>-Fault Model.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2006

Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2006

A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.

[BibT_eX]

[DOI]

Khader S. Abdel-Hafez

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Test Cost Reduction Using Partitioned Grid Random Access Scan.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Analytic modeling of detection latency in mobile sensor networks.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on Information Processing in Sensor Networks, 2006

Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Optimal Sensor Distribution for Maximum Exposure in A Region with Obstacles.

[BibT_eX]

[DOI]

Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

Diagnosis of Transistor Shorts in Logic Test Environment.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Optimizing program disturb fault tests using defect-based testing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Combinational automatic test pattern generation for acyclic sequential circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Efficient Test Set Modification for Capture Power Reduction.

[BibT_eX]

[DOI]

J. Low Power Electron., 2005

Fault Diagnosis of Physical Defects Using Unknown Behavior Model.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2005

On Design for I<sub>DDQ</sub>-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2005

Delay Fault Testing of Processor Cores in Functional Mode.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2005

Yield-Driven, False-Path-Aware Clock Skew Scheduling.

[BibT_eX]

[DOI]

Jeng-Liang Tsai

Charlie Chung-Ping Chen

IEEE Des. Test Comput., 2005

On Low-Capture-Power Test Generation for Scan Testing.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

False Path and Clock Scheduling Based Yield-Aware Gate Sizing.

[BibT_eX]

[DOI]

Jeng-Liang Tsai

Charlie Chung-Ping Chen

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Exposure for collaborative detection using mobile sensor networks.

[BibT_eX]

[DOI]

Kuang-Ching Wang

Proceedings of the IEEE 2nd International Conference on Mobile Adhoc and Sensor Systems, 2005

Low-capture-power test generation for scan-based at-speed testing.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Design and analysis of multiple weight linear compactors of responses containing unknown values.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Progressive random access scan: a simultaneous solution to test power, test data volume and test time.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Instruction-based delay fault self-testing of pipelined processor cores.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Testing Superscalar Processors in Functional Mode.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

A Class of Linear Space Compactors for Enhanced Diagnostic.

[BibT_eX]

[DOI]

Hideo Fujiwara

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Fault Tolerance in Collaborative Sensor Networks for Target Detection.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2004

Instruction-Based Delay Fault Self-Testing of Processor Cores.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Static Timing Analysis of Irreversible Crosstalk Noise Pulse Faults.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Random Access Scan: A solution to test power, test data volume and test time.

[BibT_eX]

[DOI]

Seiji Kajihara

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Testing Micropipelined Asynchronous Circuits.

[BibT_eX]

[DOI]

Matthew L. King

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Testing of Hard Faults in Simultaneous Multithreaded Processors.

[BibT_eX]

[DOI]

T. M. Mak

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

On per-test fault diagnosis using the X-fault model.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A yield improvement methodology using pre- and post-silicon statistical clock scheduling.

[BibT_eX]

[DOI]

Jeng-Liang Tsai

Charlie Chung-Ping Chen

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values.

[BibT_eX]

[DOI]

Seiji Kajihara

Proceedings of the 9th European Test Symposium, 2004

2003

Sensor Deployment Strategy for Detection of Targets Traversing a Region.

[BibT_eX]

[DOI]

Veradej Phipatanasuphorn

Mob. Networks Appl., 2003

Electrical Model For Program Disturb Faults in Non-Volatile Memories.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Exclusive Test and its Applications to Fault Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Fault Diagnosis for Physical Defects of Unknown Behaviors.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Software-Based Delay Fault Testing of Processor Cores.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Stress Test for Disturb Faults in Non-Volatile Memories.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Minimizing Energy Consumption for High-Performance Processing.

[BibT_eX]

[DOI]

Mikko H. Lipasti

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Estimation of Maximum Power-Up Current.

[BibT_eX]

[DOI]

Fei Li

Lei He

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Multiple Faults: Modeling, Simulation and Test.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets.

[BibT_eX]

[DOI]

Hiroshi Takahashi

Yuzo Takamatsu

Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002

Sensor deployment strategy for target detection.

[BibT_eX]

[DOI]

Veradej Phipatanasuphorn

Proceedings of the First ACM International Workshop on Wireless Sensor Networks and Applications, 2002

A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Fault Models and Test Procedures for Flash Memory Disturbances.

[BibT_eX]

[DOI]

Alex S. Yap

J. Electron. Test., 2001

Flash Memory Disturbances: Modeling and Test.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Testable Sequential Circuit Design: A Partition and Resynthesis Approach.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Efficient Signature-Based Fault Diagnosis Using Variable Size Windows.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Combinational test generation for various classes of acyclic sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Static test compaction for IDDQ testing of bridging faults in sequential circuits.

[BibT_eX]

[DOI]

Syst. Comput. Jpn., 2000

Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Testing Flash Memories.

[BibT_eX]

[DOI]

Alex S. Yap

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Fault Tolerance through Re-Execution in Multiscalar Architecture.

[BibT_eX]

[DOI]

Faisal Rashid

Proceedings of the 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 2000

Fault models and test generation for IDDQ testing: embedded tutorial.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

1999

Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits.

[BibT_eX]

[DOI]

Yoshinobu Higami

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability.

[BibT_eX]

[DOI]

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

A Novel Approach to Random Pattern Testing of Sequential Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1998

Sequential test generators: past, present and future.

[BibT_eX]

[DOI]

Integr., 1998

A Heuristic Measure to Maximize Detected Faults per Test.

[BibT_eX]

[DOI]

J. Electron. Test., 1998

On Test Pattern Compaction Using Random Pattern Fault Simulation.

[BibT_eX]

[DOI]

Seiji Kajihara

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Design for Diagnosability of CMOS Circuits.

[BibT_eX]

[DOI]

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits.

[BibT_eX]

[DOI]

Yoshinobu Higami

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Scheduling tests for VLSI systems under power constraints.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1997

Guest Editorial.

[BibT_eX]

[DOI]

Kwang-Ting Cheng

Hans-Joachim Wunderlich

J. Electron. Test., 1997

Sequential Circuit Testing: From DFT to SFT.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits.

[BibT_eX]

[DOI]

VLSI Design, 1996

Incorporating performance and testability constraints during binding in high-level synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Methods for Dynamic Test Vector compaction in Sequential Test Generation.

[BibT_eX]

[DOI]

Timothy John Lambert

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A new method towards achieving global optimality in technology mapping.

[BibT_eX]

[DOI]

Xiaoqing Wen

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Random Pattern Testing for Sequential Circuits Revisited.

[BibT_eX]

[DOI]

Proceedings of the Digest of Papers: FTCS-26, 1996

1995

Test application time reduction for sequential circuits with scan.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

An optimized testable architecture for finite state machines.

[BibT_eX]

[DOI]

Ting-Yu Kuo

Chun-Yeh Liu

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Fast computation of MISR signatures.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Test application time reduction for scan based sequential circuits.

[BibT_eX]

[DOI]

Hao Zheng

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan.

[BibT_eX]

[DOI]

Ning Jiang

Proceedings of the Digest of Papers: FTCS-25, 1995

1994

Hypergraph Coloring and Reconfigured RAM Testing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1994

On-chip testing of random access memories.

[BibT_eX]

[DOI]

J. Electron. Test., 1994

Incorporating testability considerations in high-level synthesis.

[BibT_eX]

[DOI]

J. Electron. Test., 1994

Sequential test generation with reduced test clocks for partial scan designs.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

An Algorithm to Test Reconfigured RAMs.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on VLSI Design, 1994

Power Constraint Scheduling of Tests.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on VLSI Design, 1994

Behavioral Synthesis of Testable Designs.

[BibT_eX]

[DOI]

Proceedings of the Digest of Papers: FTCS/24, 1994

1993

Theory, Analysis and Implementation of an On-Line BIST Technique.

[BibT_eX]

[DOI]

Rajiv Sharma

VLSI Design, 1993

An efficient algorithm for bipartite PLA folding.

[BibT_eX]

[DOI]

Chun-Yeh Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

An Efficient Algorithm for Sequential Circuit Test Generation.

[BibT_eX]

[DOI]

Todd P. Kelsey

IEEE Trans. Computers, 1993

A Tutorial on Built-In Self-Test, Part 2: Applications.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1993

A Tutorial on Built-in Self-Test. I. Principles.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1993

CCSTG: an efficient test pattern generator for sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Efficient Test Vectors for ISCAS Sequential Benchmark Circuits.

[BibT_eX]

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992

An Efficient Signature Computation Method.

[BibT_eX]

[DOI]

Chin-Foo See

IEEE Des. Test Comput., 1992

Zero cost testing of check bits in RAMs with on-chip ECC.

[BibT_eX]

[DOI]

Michael J. Franklin

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

On fault deletion problem in concurrent fault simulation for synchronous sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

An Efficient Method for Computation of Signatures.

[BibT_eX]

[DOI]

Chin-Foo See

Proceedings of the Fifth International Conference on VLSI Design, 1992

An algorithm to reduce test application time in full scan designs.

[BibT_eX]

[DOI]

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Incorporating Testability Considerations in High-Level Systhesis.

[BibT_eX]

[DOI]

Proceedings of the Digest of Papers: FTCS-22, 1992

1991

A method of reducing aliasing in a built-in self-test environment.

[BibT_eX]

[DOI]

Keiho Akiyama

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

An Algorithm to Test Rams for Physical Neighborhood Pattern Sensitive Faults.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Pattern Sensitive Fault Testing of RAMs with Bullt-in ECC.

[BibT_eX]

[DOI]

Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

1990

Design and Analysis of a Gracefully Degrading Interleaved Memory System.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1990

Improved Test Generation for High-Activity Circuits.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1990

Built-in Self-testing of Random-Access Memories.

[BibT_eX]

[DOI]

Computer, 1990

1989

Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1989, 1989

Fast test generation for sequential circuits.

[BibT_eX]

[DOI]

Todd P. Kelsey

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

A study of time-redundant fault tolerance techniques for high-performance pipelined computers.

[BibT_eX]

[DOI]

Gurindar S. Sohi

Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

Row/column pattern sensitive fault detection in RAMs via built-in self-test.

[BibT_eX]

[DOI]

Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1988

A new approach to the design of built-in self-testing PLAs for high fault coverage.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

A concurrent testing technique for digital circuits.

[BibT_eX]

[DOI]

Rajiv Sharma

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

An experimental study to determine task size for rollback recovery systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1988

A Data Compression Technique for Built-In Self-Test.

[BibT_eX]

[DOI]

Mark G. Karpovsky

IEEE Trans. Computers, 1988

Test Scheduling and Control for VLSI Built-In Self-Test.

[BibT_eX]

[DOI]

Gary L. Craig

IEEE Trans. Computers, 1988

An implementation and analysis of a concurrent built-in self-test technique.

[BibT_eX]

[DOI]

Rajiv Sharma

Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

1987

Built-In Self-Testing RAM: A Practical Alternative.

[BibT_eX]

[DOI]

Siew H. Sng

IEEE Des. Test, 1987

Organization and Analysis of a Gracefully-Degrading Interleaved Memory System.

[BibT_eX]

[DOI]

Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987

BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays.

[BibT_eX]

[DOI]

Chun-Yeh Liu

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986

A Wachtdog Processor Based General Rollback Technique with Multiple Retries.

[BibT_eX]

[DOI]

IEEE Trans. Software Eng., 1986

Testable Design of Single-Output Sequential Machines Using Checking Experiments.

[BibT_eX]

[DOI]

Ramaswami Dandapani

IEEE Trans. Computers, 1986

An Alternative to Scan Design Methods for Sequential Machines.

[BibT_eX]

[DOI]

Ramaswami Dandapani

IEEE Trans. Computers, 1986

Built-In Testing of Memory Using an On-Chip Compact Testing Scheme.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1986

A Novel Approach for Testing Memories Using a Built-In Self Testing Technique.

[BibT_eX]

Proceedings of the Proceedings International Test Conference 1986, 1986

1985

Test Pattern Generation for API Faults in RAM.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1985

Design of Programmable Logic Arrays for Parallel Testing.

[BibT_eX]

C. Boswell

Comput. Syst. Sci. Eng., 1985

A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead.

[BibT_eX]

Hideo Fujiwara

Proceedings of the Proceedings International Test Conference 1985, 1985

1984

Testable design of large random access memories.

[BibT_eX]

[DOI]

Kim Thang Le

Integr., 1984

Built-in Testing of Memory Using On-chip Compact Testing Scheme.

[BibT_eX]

Proceedings of the Proceedings International Test Conference 1984, 1984

1983

An Easily Testable Design of Programmable Logic Arrays for Multiple Faults.

[BibT_eX]

[DOI]

Hideo Fujiwara

IEEE Trans. Computers, 1983

A Simplified Algorithm for Testing Microprocessors.

[BibT_eX]

Li Shen

Stephen Y. H. Su

Proceedings of the Proceedings International Test Conference 1983, 1983

Testing Computer Hardware through Data Compression in Space and Time.

[BibT_eX]

Mark G. Karpovsky

Proceedings of the Proceedings International Test Conference 1983, 1983

1982

An enhancement of lssd to reduce test pattern generation effort and increase fault coverage.

[BibT_eX]

[DOI]

Proceedings of the 19th Design Automation Conference, 1982

1980

Synchronous Sequential Machines: A Modular and Testable Design.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1980

Fault diagnosis in loop-connected systems.

[BibT_eX]

[DOI]

Brian D. O. Anderson

Inf. Sci., 1980

1979

Minimization of Reed-Muller Canonic Expansion.

[BibT_eX]

[DOI]

E. H. Ong

IEEE Trans. Computers, 1979

1975

Fault Detecting Test Sets for Reed-Muller Canonic Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1975

1974

Easily Testable Two-Dimensional Cellular Logic Arrays.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1974

On Minimally Testable Logic Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1974

1972

Multiple Faults in Reed-Muller Canonic Networks

[BibT_eX]

[DOI]