Kevin W. Gorman

According to our database1, Kevin W. Gorman authored at least 10 papers between 2004 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
Practical Application of RAM Sequential Test.
IEEE Des. Test, 2016

2015
Optimizing delay tests at the memory boundary.
Proceedings of the 2015 IEEE International Test Conference, 2015

2011
Embedded DRAM in 45-nm Technology and Beyond.
IEEE Des. Test Comput., 2011

2007
Synchronous collaborative systems for distributed virtual environments in Java.
Int. J. Comput. Appl. Technol., 2007

Advancements in at-speed array BIST: multiple improvements.
Proceedings of the 2007 IEEE International Test Conference, 2007

A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Low Cost Test of High Bandwidth Embedded Memories.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining.
IEEE J. Solid State Circuits, 2005

Synchronization methods for supporting distributed 3D virtual environments in Java<sup>TM</sup>.
Proceedings of the International Conference on Advances in Computer Entertainment Technology, 2005

2004
Generating At-Speed Array Fail Maps with Low-Speed ATE.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004


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