Kevin Tshun Chuan Chai
Orcid: 0000-0001-6624-8912Affiliations:
- A*STAR, Singapore
According to our database1,
Kevin Tshun Chuan Chai
authored at least 28 papers
between 2014 and 2024.
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Bibliography
2024
A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024
2023
A 35mW, 2.32dB NF, 1.1° Phase Error, 18-21.2GHz Beamforming Receiver IC for Satcom on the Move (SOTM) Phased Arrays.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
A 29-31-GHz, 0.4-dB Amplitude Error and 1° Phase Error Beamforming IC and 20-dB Dynamic Range Power Detector for SatCom Phased Arrays.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array.
IEEE J. Solid State Circuits, 2023
1V, 1.13μm pixel pitch Liquid Crystal Driver with Charge-Balancing Scheme for SLM Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Continuous-Time Ising Machine using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks.
IEEE J. Solid State Circuits, 2022
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Linearity Characterization of Hybrid Driving Scheme for Spatial Light Modulator System.
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific Simulations.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks.
Proceedings of the International SoC Design Conference, 2020
A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
IEEE Trans. Ind. Electron., 2019
Learning of Multi-Dimensional Analog Circuits Through Generative Adversarial Network (GAN).
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
2017
A passively compensated capacitive sensor readout with biased varactor temperature compensation and temperature coherent quantization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A 1.2 V, 0.84 pJ/conv.-Step ultra-low power capacitance to digital converter for microphone based auscultation.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
Proceedings of the International Symposium on Integrated Circuits, 2016
Proceedings of the International Symposium on Integrated Circuits, 2016
A 65-nm 0.35-V 7.1-μW memory-less adaptive PCG processor for wearable long-term cardiac monitoring.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A Time-Domain Band-Gap Temperature Sensor in SOI CMOS for High-Temperature Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014