Kevin J. Nowka
Orcid: 0000-0002-5130-8318
According to our database1,
Kevin J. Nowka
authored at least 59 papers
between 1995 and 2024.
Collaborative distances:
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Bibliography
2024
Testing the Performance of LSTM and ARIMA Models for In-Season Forecasting of Canopy Cover (CC) in Cotton Crops.
Remote. Sens., June, 2024
Cotton yield prediction utilizing unmanned aerial vehicles (UAV) and Bayesian neural networks.
Comput. Electron. Agric., 2024
2023
Proceedings of the 21st IEEE/ACIS International Conference on Software Engineering Research, 2023
A Deep Transfer Learning based approach for forecasting spatio-temporal features to maximize yield in cotton crops.
Proceedings of the 57th Annual Conference on Information Sciences and Systems, 2023
2015
2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
2010
J. Electron. Test., 2010
Proceedings of the 2010 International Symposium on Physical Design, 2010
Technology variability and uncertainty implications for power- efficient VLSI systems.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the ESSCIRC 2008, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
A dual-V<sub>DD</sub> boosted pulsed bus technique for low power and low leakage operation.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
2005
IEEE Des. Test Comput., 2005
Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
2004
IEEE J. Solid State Circuits, 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
A low latency and low power dynamic Carry Save Adder.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 41th Design Automation Conference, 2004
2003
IBM J. Res. Dev., 2003
Evaluation of Dynamic-Threshold Logic for Low-Power VLSI Design in 0.13um PD-SOI.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
J. VLSI Signal Process., 2002
A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling.
IEEE J. Solid State Circuits, 2002
2001
Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001
2000
IBM J. Res. Dev., 2000
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000
1999
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
1998
IEEE J. Solid State Circuits, 1998
High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
1997
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997
1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995