Kevin J. M. Martin
Orcid: 0000-0002-8122-1192Affiliations:
- University of Southern Brittany, France
- University of Rennes 1, France (PhD 2010)
According to our database1,
Kevin J. M. Martin
authored at least 44 papers
between 2009 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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on orcid.org
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Bibliography
2024
IEEE Trans. Parallel Distributed Syst., July, 2024
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024
Proceedings of the Design and Architectures for Signal and Image Processing, 2024
Scratchy: A Class of Adaptable Architectures with Software-Managed Communication for Edge Streaming Applications.
Proceedings of the Design and Architectures for Signal and Image Processing, 2024
2023
ACM Trans. Embed. Comput. Syst., 2023
Mapping parallel applications on parallel architectures: Granularity of parallelism and synchronisation.
, 2023
2022
J. Signal Process. Syst., 2022
J. Signal Process. Syst., 2022
IEEE Trans. Parallel Distributed Syst., 2022
Mitigating Transceiver and Token Controller Permanent Faults in Wireless Network-on-Chip.
Proceedings of the 30th Euromicro International Conference on Parallel, 2022
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022
ManyGUI: A Graphical Tool to Accelerate Many-core Debugging Through Communication, Memory, and Energy Profiling.
Proceedings of the DroneSE and RAPIDO '22: System Engineering for constrained embedded systems, Budapest Hungary, January 17, 2022
2021
J. Signal Process. Syst., 2021
IEEE Trans. Parallel Distributed Syst., 2021
On Cache Limits for Dataflow Applications and Related Efficient Memory Management Strategies.
Proceedings of the DASIP '21: Workshop on Design and Architectures for Signal and Image Processing (14th edition), 2021
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021
2020
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Broadcast- and Power-Aware Wireless NoC for Barrier Synchronization in Parallel Computing.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2018
Subutai: distributed synchronization primitives in NoC interfaces for legacy parallel-applications.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
J. Signal Process. Syst., 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
Notifying memories: a case-study on data-flow applications with NoC interfaces implementation.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Improving reuse by means of asymmetrical model migrations: An application to the Orcc case study.
Proceedings of the 18th ACM/IEEE International Conference on Model Driven Engineering Languages and Systems, 2015
Compa backend: A dynamic runtime for the execution of dataflow programs onto multi-core platforms.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015
2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
Communication-model based embedded mapping of dataflow actors on heterogeneous MPSoC.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformations.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
2013
Proceedings of the 13th IEEE International Working Conference on Source Code Analysis and Manipulation, 2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
2012
Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation.
ACM Trans. Reconfigurable Technol. Syst., 2012
2010
Génération automatique d'extensions de jeux d'instructions de processeurs. (Automatic Generation of Instruction-set Extensions).
PhD thesis, 2010
2009
Constraint-Driven Identification of Application Specific Instructions in the <i>DURASE</i> System.
Proceedings of the Embedded Computer Systems: Architectures, 2009
How Constrains Programming Can Help You in the Generation of Optimized Application Specific Reconfigurable Processor Extensions.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009