Kevin J. Chen

Orcid: 0000-0002-0659-2022

Affiliations:
  • Hong Kong University of Science and Technology, Department of Electronic and Computer Engineering, Hong Kong


According to our database1, Kevin J. Chen authored at least 19 papers between 1996 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Characteristics and Evaluation Approaches of Human-Body-Model Electrostatic Discharge Across Schottky p-GaN Gate HEMTs.
IEEE Trans. Ind. Electron., March, 2024

2022
650-V Normally-OFF GaN/SiC Cascode Device for Power Switching Applications.
IEEE Trans. Ind. Electron., 2022

I<sub>G</sub>- and V<sub>GS</sub>-Dependent Dynamic R<sub>ON</sub> Characterization of Commercial High-Voltage p-GaN Gate Power HEMTs.
IEEE Trans. Ind. Electron., 2022

Monolithic Integration of Gate Driver and Protection Modules With P-GaN Gate Power HEMTs.
IEEE Trans. Ind. Electron., 2022

Short-Circuit Failure Mechanisms of 650-V GaN/SiC Cascode Devices in Comparison With SiC MOSFETs.
IEEE Trans. Ind. Electron., 2022

Short-Circuit Characteristics and High-Current Induced Oscillations in a 1200-V/80-mΩ Normally-Off SiC/GaN Cascode Device.
IEEE Trans. Ind. Electron., 2022

2021
Short Circuit Capability Characterization and Analysis of p-GaN Gate High-Electron-Mobility Transistors Under Single and Repetitive Tests.
IEEE Trans. Ind. Electron., 2021

E-mode p-FET-bridge HEMT: Toward high VTH, low reverse-conduction loss and enhanced stability.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
Characterization of Static and Dynamic Behavior of 1200 V Normally off GaN/SiC Cascode Devices.
IEEE Trans. Ind. Electron., 2020

2019
Reverse-Bias Stability and Reliability of Enhancement-mode GaN-based MIS-FET.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
High-performance Enhancement-mode GaN Power MIS-FET with Interface Protection Layer.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

2015
An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014
Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2010
Residual stress characterization of GaN microstructures using bent-beam strain sensors.
Proceedings of the 5th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2010

2006
Enhancement-Mode AlGaN/GaN HEMTs with Low On-Resistance and Low Knee-Voltage.
IEICE Trans. Electron., 2006

2003
Logic synthesis and circuit modeling of a programmable logic gate based on controlled quenching of series-connected negative differential resistance devices.
IEEE J. Solid State Circuits, 2003

Silicon-on-organic integration of a 2.4GHz VCO using high Q copper inductors and solder-bumped flip chip technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

1998
Resonant-tunneling diode and HEMT logic circuits with multiple thresholds and multilevel output.
IEEE J. Solid State Circuits, 1998

1996
A Literal Gate Using Resonant-Tunneling Devices.
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996


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