Kevin Garello

Orcid: 0000-0003-0236-322X

According to our database1, Kevin Garello authored at least 8 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses.
CoRR, 2023

2020
Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018
SOT-MRAM 300mm integration for low power and ultrafast embedded memories.
CoRR, 2018

SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2016
Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing.
IEEE Trans. Multi Scale Comput. Syst., 2016


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