Kevin Chung

Orcid: 0000-0002-1747-3491

According to our database1, Kevin Chung authored at least 16 papers between 1990 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
Social Structures and Reputation in Expert Review Systems.
Manag. Sci., 2020

Incorporating a "Better" Behavioral Bias for Both Consumers and Firms in Rebate Programs.
Manag. Sci., 2020

2019
Third-Party Reviews and Quality Provision.
Manag. Sci., 2019

Towards Tattoo Previewing and Other Augmented/Mixed Reality Applications with Microsoft Kinect.
Proceedings of the IEEE 9th Annual Computing and Communication Workshop and Conference, 2019

2017
Live Lesson: Lowering the Barriers to Capture The Flag Administration and Participation.
Proceedings of the 2017 USENIX Workshop on Advances in Security Education, 2017

2015
The Effect of Identity Disclosure on Reliability and Efforts Provision in Online Review Systems.
Proceedings of the 21st Americas Conference on Information Systems, 2015

2014
Learning Obstacles in the Capture The Flag Model.
Proceedings of the 2014 USENIX Summit on Gaming, 2014

2013
Analyzing System-Level Information's Correlation to FPGA Placement.
ACM Trans. Reconfigurable Technol. Syst., 2013

2009
WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging.
ACM Trans. Reconfigurable Technol. Syst., 2009

SmartOpt: an industrial strength framework for logic synthesis.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008
WireMap: FPGA technology mapping for improved routability.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

2000
The Effect of Constraint Notification within a Case Tool Environment of Design Productivity and Quality.
Proceedings of the Product Focused Software Process Improvement, 2000

1999
The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout.
IEEE Trans. Very Large Scale Integr. Syst., 1999

The design of an SRAM-based field-programmable gate array. I. Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 1999

1992
TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections.
Proceedings of the 29th Design Automation Conference, 1992

1990
Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990


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