Keunwoo Kim

Orcid: 0000-0003-3799-6780

According to our database1, Keunwoo Kim authored at least 33 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Enhancing Social Media Post Popularity Prediction with Visual Content.
CoRR, 2024

Codebook Design for Air-to-Air Communication Systems Operating in the UAM Corridor.
Proceedings of the IEEE International Conference on Communications Workshops, 2024

2023
Singular Direction-Based Quantizer and Receiver Designs for User Cooperative Distributed Reception.
IEEE Syst. J., March, 2023

2022
Robust Beam Management in Position and Velocity Aware V2V Communications Using Distributed Antenna Subarrays.
IEEE Trans. Veh. Technol., 2022

Adaptive Beam Design for V2I Communications Using Vehicle Tracking With Extended Kalman Filter.
IEEE Trans. Veh. Technol., 2022

Transformer Network-based Reinforcement Learning Method for Power Distribution Network (PDN) Optimization of High Bandwidth Memory (HBM).
CoRR, 2022

Joint Estimation of Vehicle's Position and Velocity With Distributed RSUs for OFDM Radar System.
Proceedings of the IEEE Global Communications Conference, 2022

Outdoor Localization Based on RSS Ranging Aided by Pedestrian Dead Reckoning in GPS Restricted Scenario.
Proceedings of the IEEE VTS Asia Pacific Wireless Communications Symposium, 2022

2021
Hurdle Relay: A Participatory Design Method for Understanding the Information Gap Through Iterative Comparison.
Proceedings of the HCI International 2021 - Posters - 23rd HCI International Conference, 2021

Guiding Preferred Driving Style Using Voice in Autonomous Vehicles: An On-Road Wizard-of-Oz Study.
Proceedings of the DIS '21: Designing Interactive Systems Conference 2021, 2021

2015
Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2014
Impact of FinFET technology for power gating in nano-scale design.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2012
Assessment of structure variation in silicon nanowire FETs and impact on SRAM.
Microelectron. J., 2012

2010
FinFET SRAM Design.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Technology-circuit co-design of asymmetric SRAM cells for read stability improvement.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Yield estimation of SRAM circuits using "Virtual SRAM Fab".
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008
Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2008

An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process.
IEEE J. Solid State Circuits, 2008

Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Variability Analysis for sub-100nm PD/SOI Sense-Amplifier.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices.
Microelectron. J., 2007

A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

2006
Modeling and Analysis of Leakage Currents in Double-Gate Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2005
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

2004
Nanoscale CMOS circuit leakage power reduction by double-gate device.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003
Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Strained-si devices and circuits for low-power applications.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003


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