Kesami Hagiwara

According to our database, Kesami Hagiwara authored at least 2 papers between 2006 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications.

Kesami Hagiwara, Tomoichi Hayashi, Shumpei Kawasaki, Fumio Arakawa, Oleg Endo, Hayato Nomura, Akira Tsukamoto, Duong Nguyen, Binh Nguyen, Anh Tran, Hoan Hyunh, Ikuo Kudoh, Cong-Kha Pham

Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

2006

Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications.

Yasuo Sugure, Seiji Takeuchi, Yuichi Abe, Hiromichi Yamada, Kazuya Hirayanagi, Akihiko Tomita, Kesami Hagiwara, Takeshi Kataoka, Takanori Shimura

IEICE Trans. Electron., 2006