Kensuke Iizuka

According to our database, Kensuke Iizuka authored at least 21 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Power Optimized Design Framework for FPGA Clusters.

Kensuke Iizuka, Kohei Ito, Ryota Yasudo, Hideharu Amano

IPSJ Trans. Syst. LSI Des. Methodol., 2024

Power analysis of an optical interconnected FPGA cluster for roadside units.

Hideharu Amano, Kensuke Iizuka

Proceedings of the IEEE International Conference on Consumer Electronics, 2024

2023

Power Analysis and Power Modeling of Directly-Connected FPGA Clusters.

Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano

IEICE Trans. Inf. Syst., December, 2023

A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search.

M. M. Imdad Ullah, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano

IEICE Trans. Inf. Syst., November, 2023

Parallel Implementation of CNN on Multi-FPGA Cluster.

Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano

IEICE Trans. Inf. Syst., July, 2023

Board Allocation Algorithm for the Resource Management System of FiC.

Takumi Inage, Kensuke Iizuka, Hideharu Amano

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Parallel Implementation of Vision Transformer on a Multi-FPGA Cluster.

Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano

Proceedings of the Eleventh International Symposium on Computing and Networking, CANDAR 2023, Matsue, Japan, November 28, 2023

2022

The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System.

Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano

IEICE Trans. Inf. Syst., December, 2022

A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA Systems.

Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano

Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

Toward a training of CNNs on a multi-FPGA system.

Aoi Hiruma, Kensuke Iizuka, Hideharu Amano

Proceedings of the 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022, 2022

Power Analysis of Directly-connected FPGA Clusters.

Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2022

2021

Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System.

Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano

IEICE Trans. Inf. Syst., 2021

Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud).

Kazuei Hironaka, Kensuke Iizuka, Miho Yamakura, Akram Ben Ahmed, Hideharu Amano

IEICE Trans. Inf. Syst., 2021

M-KUBOS/PYNQ Cluster for multi-access edge computing.

Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Kohei Ito, Yasuyu Fukushima, Mitaro Namiki, Hideharu Amano

Proceedings of the Ninth International Symposium on Computing and Networking, 2021

Hybrid Network of Packet Switching and STDM in a Multi-FPGA System.

Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2021

Implementing VTA, a tensor accelerator on Flow-in-Cloud.

Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano

Proceedings of the ACIT 2021: The 8th International Virtual Conference on Applied Computing & Information Technology, Kanazawa, Japan, June 20, 2021

2020

A Method of Partitioning Convolutional Layer to Multiple FPGAs.

Kensuke Iizuka, Kohei Ito, Kazuei Hironaka, Hideharu Amano

Proceedings of the International SoC Design Conference, 2020

Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system.

Yugo Yamauchi, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano

Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System.

Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano

Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

2019

An ARM-based heterogeneous FPGA accelerator for Hall thruster simulation.

Hiroyuki Noda, Manfred Orsztynowicz, Kensuke Iizuka, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano

Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019

Demonstration of Flow-in-Cloud: A Multi-FPGA System.

Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M. M. Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma, Hideharu Amano

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019