Kenneth M. Butler
According to our database1,
Kenneth M. Butler
authored at least 57 papers
between 1988 and 2017.
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Bibliography
2017
Accurate ADC testing with significantly relaxed instrumentation including large cumulative jitter.
Proceedings of the IEEE International Test Conference, 2017
2016
Proceedings of the 2016 IEEE International Test Conference, 2016
What we know after twelve years developing and deploying test data analytics solutions.
Proceedings of the 2016 IEEE International Test Conference, 2016
2015
A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling.
Proceedings of the 2014 International Test Conference, 2014
2013
Per-Device Adaptive Test for Analog/RF Circuits Using Entropy-Based Process Monitoring.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
J. Electron. Test., 2013
Test data analytics - Exploring spatial and test-item correlations in production test data.
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Proceedings of the 2011 IEEE International Test Conference, 2011
Proceedings of the 2011 IEEE International Test Conference, 2011
Proceedings of the 2011 IEEE International Test Conference, 2011
2010
Adaptive test flow for mixed-signal/RF circuits using learned information from device under test.
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Proceedings of the 27th International Conference on Computer Design, 2009
2008
Proceedings of the 2008 IEEE International Test Conference, 2008
2007
Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Des. Test Comput., 2007
2006
IEEE Des. Test Comput., 2006
2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
2003
IEEE Des. Test Comput., 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
2001
IEEE Des. Test Comput., 2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
1999
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
A study of test quality/tester scan memory trade-offs using the SEMATECH test methods data.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
1997
An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
1994
Correlating defect level to final test fault coverage for modular structured designs [microcontroller family].
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994
1992
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992
1991
Exact ordered binary decision diagram size when representing classes of symmetric functions.
J. Electron. Test., 1991
Proceedings of the conference on European design automation, 1991
Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams.
Proceedings of the 28th Design Automation Conference, 1991
1990
The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990
1988
CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988