Kenji Taniguchi
Affiliations:- Osaka University, Japan
According to our database1,
Kenji Taniguchi
authored at least 55 papers
between 1985 and 2013.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1998, "For contributions to the development of MOS device fabrication processes, particularly dielectric breakdown and oxygen-enhanced diffusion.".
Timeline
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Bibliography
2013
IEICE Electron. Express, 2013
2012
A High Dynamic Range and Low Power Consumption Audio Delta-Sigma Modulator with Opamp Sharing Technique among Three Integrators.
IEICE Trans. Electron., 2012
IEICE Electron. Express, 2012
A novel RC time constant tuning technique utilizing programmable current sources for continuous-time delta-sigma modulators.
IEICE Electron. Express, 2012
2011
IEEE Trans. Consumer Electron., 2011
A Multi-Stage Second Order Dynamic Element Matching with In-Band Mismatch Noise Reduction Enhancement.
IEICE Trans. Electron., 2011
A Dynamic Dither Gain Control Technique for Multi-Level Delta-Sigma DACs with Multi-Stage Second Order Dynamic Element Matching.
IEICE Trans. Electron., 2011
A Wide Dynamic Range Variable Gain Amplifier with Enhanced IP1 dB and Temperature Compensation.
IEICE Trans. Electron., 2011
IEICE Trans. Electron., 2011
Design of a 500-MS/s stochastic signal detection circuit using a non-linearity reduction technique in a 65-nm CMOS process.
IEICE Electron. Express, 2011
IEICE Electron. Express, 2011
A 7.5mW 101dB SNR low-power high-performance audio delta-sigma modulator utilizing opamp sharing technique.
Proceedings of the International SoC Design Conference, 2011
2010
IEEE Trans. Consumer Electron., 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Trans. Electron., 2010
IEICE Electron. Express, 2010
2009
A Reference Voltage Buffer with Settling Boost Technique for a 12 bit 18 MHz Multibit/Stage Pipelined A/D Converter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
IEICE Trans. Electron., 2009
Application of Noise-Enhanced Detection of Subthreshold Signals for Communication Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
IEICE Trans. Electron., 2008
A novel third order Delta Sigma Modulator with one opamp shared among three integrator stages.
IEICE Electron. Express, 2008
IEICE Electron. Express, 2008
Sub-threshold signal detection using noise statistics for communications applications.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
2006
Analytical GMD formulas for mutual inductance calculation of multilevel interconnects.
IEICE Electron. Express, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2005
A New Inductance Extraction Technique of On-Wafer Spiral Inductor Based on Analytical Interconnect Formula.
IEICE Trans. Electron., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Electron., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Electron. Express, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
IEICE Electron. Express, 2004
IEICE Electron. Express, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
CMOS voltage reference based on gate work function differences in poly-Si controlled by conductivity type and impurity concentration.
IEEE J. Solid State Circuits, 2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Multiple-bit parallel-CDMA technique for an on-chip interface featuring high data transmission rate, small latency and high noise tolerance.
Proceedings of the ESSCIRC 2003, 2003
2002
A study of robustness and coupling-noise immunity on simultaneous data transfer CDMA bus interface.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
A novel dynamically programmable arithmetic array using code division multiple access bus.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
1990
Process modeling and simulation: boundary conditions for point defect-based impurity diffusion model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990
1985
Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985