Kenji Shimazaki

According to our database, Kenji Shimazaki authored at least 13 papers between 2000 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

Gate Delay Estimation in STA under Dynamic Power Supply Noise.

Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

2009

A minimum decap allocation technique based on simultaneous switching for nanoscale SoC.

Kenji Shimazaki, Takaaki Okumura

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2006

An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs.

Kenji Shimazaki, Makoto Nagata, Mitsuya Fukazawa, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa

IEICE Trans. Electron., 2006

2005

Power-Supply Noise Reduction with Design for Manufacturability.

Hiroyuki Tsujikawa, Kenji Shimazaki, Shozo Hirano, Kazuhiro Sato, Masanori Hirofuji, Junichi Shimada, Mitsumi Ito, Kiyohito Mukai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits.

Kenji Shimazaki, Makoto Nagata, Takeshi Okumoto, Shozo Hirano, Hiroyuki Tsujikawa

IEICE Trans. Electron., 2005

An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs.

Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias.

Yoshihide Komatsu, Koichiro Ishibashi, Masaharu Yamamoto, Toshiro Tsukada, Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement.

Shen Lin, Makoto Nagata, Kenji Shimazaki, Kazuhiro Satoh, Masaya Sumita, Hiroyuki Tsujikawa, Andrew T. Yang

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

A Design Methodology for Low EMI Noise LSI with Fast and Accurate Estimation.

Hiroyuki Tsujikawa, Shozo Hirano, Kenji Shimazaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A substrate noise analysis methodology for large-scale mixed-signal ICs.

Wen Kung Chu, Nishath K. Verghese, Heayn-Jun Chol, Kenji Shimazaki, Hiroyuki Tsujikawa, Shouzou Hirano, Shirou Doushoh, Makoto Nagata, Atsushi Iwata, Takafumi Ohmoto

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

An EMI-Noise Analysis on LSI Design with Impedance Estimation.

Kenji Shimazaki, Shouzou Hirano, Hiroyuki Tsujikawa

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

A design methodology for low EMI-noise microprocessor with accurate estimation-reduction-verification.

Hiroyulu Tsujikawa, Kenji Shimazaki, Shozo Hirano, Motohiro Ohki, Talcashi Yoneda, Hiroshi Benno

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2000

LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator.

Kenji Shimazaki, Hiroyuki Tsujikawa, Seijiro Kojima, Shouzou Hirano

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000