Kenji Numata

Orcid: 0000-0001-5029-3233

According to our database1, Kenji Numata authored at least 16 papers between 1989 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Dual Laser Indium Phosphide Photonic Integrated Circuits for Remote Active Carbon Dioxide Sensing.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

Progress of the US Laser Development for the Laser Interferometer Space Antenna (LISA) Program.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2022

Adaptive Wavelength Scanning Lidar (AWSL) for 3D Mapping from Space.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2022

2021
Orbiting and In-Situ Lidars for Earth and Planetary Applications.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2021

Integrated Photonics Technology for Earth Science Remote-Sensing Lidar.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2021

2020
Orbiting and In-Situ Lidars for Earth and Planetary Applications.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2020

2019
Integrated Micro-Photonics for Remote Earth Science Sensing (Impress) Lidar.
Proceedings of the 2019 IEEE International Geoscience and Remote Sensing Symposium, 2019

2018
Fiber-Based Laser Transmitter Technology Maturation for Spectroscopic Measurements from Space.
Proceedings of the 2018 IEEE International Geoscience and Remote Sensing Symposium, 2018

2001
Interface socket design methodology to generate embedded DRAM macros.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus.
IEEE J. Solid State Circuits, 2000

1999
Universal Test Interface for Embedded-DRAM Testing.
IEEE Des. Test Comput., 1999

1998
A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator.
IEEE J. Solid State Circuits, 1998

1995
A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM.
IEEE J. Solid State Circuits, November, 1995

1989
A 45-ns 16-Mbit DRAM with triple-well structure.
IEEE J. Solid State Circuits, October, 1989

New nibbled-page architecture for high-density DRAMs.
IEEE J. Solid State Circuits, August, 1989

An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode.
IEEE J. Solid State Circuits, June, 1989


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