Kenji Kise

According to our database, Kenji Kise authored at least 80 papers between 1996 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

An Exploration of State-of-the-Art Automation Frameworks for FPGA-Based DNN Acceleration.

Fumio Hamanaka, Takashi Odan, Kenji Kise, Thiem Van Chu

IEEE Access, 2023

A remote partial-reconfigurable SoC with a RISC-V soft processor targeting low-end FPGAs.

Yuji Yamada, Nesrine Berjab, Tomohiro Yoneda, Kenji Kise

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

An open-source and GUI-capable RISC-V computer system on a low-end FPGA board.

Kenji Kise

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Resource-efficient RISC-V Vector Extension Architecture for FPGA-based Accelerators.

Md. Ashraful Islam, Kenji Kise

Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2023

2022

RVCar: An FPGA-Based Simple and Open-Source Mini Motor Car System with a RISC-V Soft Processor.

Takuto Kanamori, Takashi Odan, Kazuki Hirohata, Kenji Kise

IEICE Trans. Inf. Syst., December, 2022

An Efficient Resource Shared RISC-V Multicore Architecture.

Md. Ashraful Islam, Kenji Kise

IEICE Trans. Inf. Syst., September, 2022

2021

A function-rich FPGA system of camera image processing for video meeting.

Takashi Odan, Takuto Kanamori, Kenji Kise

Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

RVCoreP-32IC: An optimized RISC- V soft processor supporting the compressed instructions.

Takuto Kanamori, Kenji Kise

Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

Efficient Resource Shared RISC-V Multicore Processor.

Md. Ashraful Islam, Kenji Kise

Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

A Low Cost and Portable Mini Motor Car System with a BNN Accelerator on FPGA.

Fumio Hamanaka, Takuto Kanamori, Kenji Kise

Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

2020

RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining.

Hiromu Miyazaki, Takuto Kanamori, Md. Ashraful Islam, Kenji Kise

IEICE Trans. Inf. Syst., 2020

High-Performance and Hardware-Efficient Odd-Even Based Merge Sorter.

Elsayed A. Elsayed, Kenji Kise

IEICE Trans. Inf. Syst., 2020

RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions.

Takuto Kanamori, Hiromu Miyazaki, Kenji Kise

CoRR, 2020

RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors.

Md. Ashraful Islam, Hiromu Miyazaki, Kenji Kise

CoRR, 2020

A portable and Linux capable RISC-V computer system in Verilog HDL.

Junya Miura, Hiromu Miyazaki, Kenji Kise

CoRR, 2020

Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs.

Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019

LEF: An Effective Routing Algorithm for Two-Dimensional Meshes.

Thiem Van Chu, Kenji Kise

IEICE Trans. Inf. Syst., 2019

An Efficient Implementation of a TAGE Branch Predictor for Soft Processors on FPGA.

Katsunoshin Matsui, Md. Ashraful Islam, Kenji Kise

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

Towards an Efficient Hardware Architecture for Odd-Even Based Merge Sorter.

Elsayed A. Elsayed, Kenji Kise

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

An Efficient Instruction Fetch Architecture for a RISC-V Soft Processor on an FPGA.

Hiromu Miyazaki, Junya Miura, Kenji Kise

Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019

2018

ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment.

Shimpei Sato, Ryohei Kobayashi, Kenji Kise

IEICE Trans. Inf. Syst., 2018

Design and Evaluation of a Configurable Hardware Merge Sorter for Various Output Records.

Elsayed A. Elsayed, Kenji Kise

Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

An Efficient Parallel Hardware Scheme for Solving the N-Queens Problem.

Yuuma Azuma, Hayato Sakagami, Kenji Kise

Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

Swap Based Merge Network for High Performance Sorting Accelerators.

Kenji Kise

Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

Very Massive Hardware Merge Sorter.

Makoto Saitoh, Kenji Kise

Proceedings of the International Conference on Field-Programmable Technology, 2018

An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs.

Thiem Van Chu, Kenji Kise

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath.

Makoto Saitoh, Elsayed A. Elsayed, Thiem Van Chu, Susumu Mashimo, Kenji Kise

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017

Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA.

Thiem Van Chu, Shimpei Sato, Kenji Kise

ACM Trans. Reconfigurable Technol. Syst., 2017

A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism.

Ryohei Kobayashi, Kenji Kise

IEICE Trans. Inf. Syst., 2017

Enhanced Long Edge First Routing Algorithm and Evaluation in Large-Scale Networks-on-Chip.

Thiem Van Chu, Myeonggu Kang, Shi Fa, Kenji Kise

Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

High-Performance Hardware Merge Sorter.

Susumu Mashimo, Thiem Van Chu, Kenji Kise

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2016

Cost-Effective and High-Throughput Merge Network: Architecture for the Fastest FPGA Sorting Accelerator.

Susumu Mashimo, Thiem Van Chu, Kenji Kise

SIGARCH Comput. Archit. News, 2016

A High-speed Verilog HDL Simulation Method using a Lightweight Translator.

Ryohei Kobayashi, Tomohiro Misono, Kenji Kise

SIGARCH Comput. Archit. News, 2016

The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs.

Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda

Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

A Cost-Effective and Scalable Merge Sorter Tree on FPGAs.

Takuma Usui, Thiem Van Chu, Kenji Kise

Proceedings of the Fourth International Symposium on Computing and Networking, 2016

An Effective Page Padding Method for RAM Buffer Algorithms to Enhance the SSD Endurance.

Eri Ogawa, Kenji Kise

Proceedings of the Fourth International Symposium on Computing and Networking, 2016

2015

Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs.

Shinya Takamaeda-Yamazaki, Hiroshi Nakatsuka, Yuichiro Tanaka, Kenji Kise

IEICE Trans. Inf. Syst., 2015

Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and Research.

Eri Ogawa, Yuki Matsuda, Tomohiro Misono, Ryohei Kobayashi, Kenji Kise

Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core Systems.

Ryohei Kobayashi, Kenji Kise

Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Effective Parallel Simulation of ArchHDL under Manycore Environment.

Tomohiro Misono, Ryohei Kobayashi, Shimpei Sato, Kenji Kise

Proceedings of the Third International Symposium on Computing and Networking, 2015

A Challenge for an Efficient AMI-based Cache System on FPGA Soft Processors.

Yuki Matsuda, Ryosuke Sasakawa, Kenji Kise

Proceedings of the Third International Symposium on Computing and Networking, 2015

Ultra-fast NoC emulation on a single FPGA.

Thiem Van Chu, Shimpei Sato, Kenji Kise

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA.

Thiem Van Chu, Shimpei Sato, Kenji Kise

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Dependable real-time task execution scheme for a many-core platform.

Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Kenji Kise

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

A Challenge of Portable and High-Speed FPGA Accelerator.

Takuma Usui, Ryohei Kobayashi, Kenji Kise

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

ArchHDL: A Novel Hardware RTL Design Environment in C++.

Shimpei Sato, Kenji Kise

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014

A framework for efficient rapid prototyping by virtually enlarging FPGA resources.

Shinya Takamaeda-Yamazaki, Kenji Kise

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Design and Performance Evaluation of a Manycore Processor for Large FPGA.

Haruka Mori, Kenji Kise

Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

KNoCEmu: High Speed FPGA Emulator for Kilo-node Scale NoCs.

Thiem Van Chu, Shimpei Sato, Kenji Kise

Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms.

Shinya Takamaeda-Yamazaki, Kenji Kise

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Ultrasmall: The smallest MIPS soft processor.

Hiroshi Nakatsuka, Yuichiro Tanaka, Thiem Van Chu, Shinya Takamaeda-Yamazaki, Kenji Kise

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

An NoC-based evaluation platform for safety-critical automotive applications.

Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

The Ultrasmall soft processor.

Yuichiro Tanaka, Shimpei Sato, Kenji Kise

SIGARCH Comput. Archit. News, 2013

LEF: long edge first routing for two-dimensional mesh network on chip.

Ryosuke Sasakawa, Kenji Kise

Proceedings of the Network on Chip Architectures, 2013

Application Aware DRAM Bank Partitioning in CMP.

Takakazu Ikeda, Kenji Kise

Proceedings of the 19th IEEE International Conference on Parallel and Distributed Systems, 2013

2012

Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations.

Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, Kenji Kise

Proceedings of the Third International Conference on Networking and Computing, 2012

CoreSymphony architecture.

Tomoyuki Nagatsuka, Yoshito Sakaguchi, Kenji Kise

Proceedings of the Computing Frontiers Conference, CF'12, 2012

ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs.

Shinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, Kenji Kise

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

An FPGA-based scalable simulation accelerator for tile architectures.

Shinya Takamaeda-Yamazaki, Ryosuke Sasakawa, Yoshito Sakaguchi, Kenji Kise

SIGARCH Comput. Archit. News, 2011

CoreSymphony: an efficient reconfigurable multi-core architecture.

Tomoyuki Nagatsuka, Yoshito Sakaguchi, Takayuki Matsumura, Kenji Kise

SIGARCH Comput. Archit. News, 2011

Rethinking processor instruction fetch: Inefficiencies-cracking mechanism.

Mochamad Asri, Naoki Fujieda, Kenji Kise

Proceedings of the International SoC Design Conference, 2011

A Partitioning Method of Cooperative Caching with Hit Frequency Counters for Many-Core Processors.

Naoki Fujieda, Kenji Kise

Proceedings of the Second International Conference on Networking and Computing, 2011

2010

Smart Core System for Dependable Many-Core Processor with Multifunction Routers.

Shinya Takamaeda, Shimpei Sato, Takefumi Miyoshi, Kenji Kise

Proceedings of the First International Conference on Networking and Computing, 2010

Pattern-Based Systematic Task Mapping for Many-Core Processors.

Shintaro Sano, Masahiro Sano, Shimpei Sato, Takefumi Miyoshi, Kenji Kise

Proceedings of the First International Conference on Networking and Computing, 2010

CODIE: Continuation-Based Overlapping Data-Transfers with Instruction Execution.

Takefumi Miyoshi, Kenji Kise, Hidetsugu Irie, Tsutomu Yoshinaga

Proceedings of the First International Conference on Networking and Computing, 2010

2009

SimCell: A Processor Simulator for Multi-Core Architecture Research.

Shimpei Sato, Naoki Fujieda, Akira Moriya, Kenji Kise

Inf. Media Technol., 2009

A Study of an Infrastructure for Research and Development of Many-Core Processors.

Koh Uehara, Shimpei Sato, Takefumi Miyoshi, Kenji Kise

Proceedings of the 2009 International Conference on Parallel and Distributed Computing, 2009

The Cache-Core Architecture to Enhance the Memory Performance on Multi-Core Processors.

Yosuke Mori, Kenji Kise

Proceedings of the 2009 International Conference on Parallel and Distributed Computing, 2009

2007

Introduction.

Kenji Kise, Toshinori Sato, Hironori Nakajo

SIGARCH Comput. Archit. News, 2007

2006

ABCLib_DRSSED: A parallel eigensolver with an auto-tuning facility.

Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba

Parallel Comput., 2006

ABCLibScript: a directive to support specification of an auto-tuning facility for numerical software.

Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba

Parallel Comput., 2006

Parallel Processing of Matrix Multiplication in a CPU and GPU Heterogeneous Environment.

Satoshi Ohshima, Kenji Kise, Takahiro Katagiri, Toshitsugu Yuba

Proceedings of the High Performance Computing for Computational Science, 2006

2005

A time-to-live based reservation algorithm on fully decentralized resource discovery in Grid computing.

Sanya Tangpongprasit, Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba

Parallel Comput., 2005

Evaluation of the Acknowledgment Reduction in a Software-DSM System.

Kenji Kise, Takahiro Katagiri, Hiroki Honda, Toshitsugu Yuba

Proceedings of the Parallel Processing and Applied Mathematics, 2005

2004

The SimCore/Alpha Functional Simulator.

Kenji Kise, Takahiro Katagiri, Hiroki Honda, Toshitsugu Yuba

Proceedings of the 2004 workshop on Computer architecture education, 2004

Effect of auto-tuning with user's knowledge for numerical software.

Takahiro Katagiri, Kenji Kise, Hiroki Honda, Toshitsugu Yuba

Proceedings of the First Conference on Computing Frontiers, 2004

2003

FIBER: A Generalized Framework for Auto-tuning Software.

Takahiro Katagiri, Kenji Kise, Hiroaki Honda, Toshitsugu Yuba

Proceedings of the High Performance Computing, 5th International Symposium, 2003

SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator.

Kenji Kise, Hiroki Honda, Toshitsugu Yuba

Proceedings of the Advances in Computer Systems Architecture, 2003

2002

DEM-1: A Particle Simulation Machine for Efficient Short-Range Interaction Computations.

Ryo Takata, Kenji Kise, Hiroki Honda, Toshitsugu Yuba

Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

1996

An efficient algorithm for the euclidean distance transformation.

Toshihiro Kato, Tomio Hirata, Toyofumi Saito, Kenji Kise

Syst. Comput. Jpn., 1996