Kenichi Ohhata

According to our database, Kenichi Ohhata authored at least 27 papers between 1989 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

High-Precision Open-Loop Time Amplifier Using Current Regulator.

Yusuke Toyoshima, Ryosuke Kamiya, Kenichi Ohhata

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022

A High-Time-Resolution Time-to-Digital Converter Using Coupled Ring Oscillator with Phase Averaging.

Daiki Ogata, Ryosuke Kamiya, Yusuke Toyoshima, Kenichi Ohhata

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

A PVT-Robust Closed-Loop Dynamic Amplifier Using Three-Stage Floating Inverter Amplifier.

Chiwen Cheng, Kenichi Ohhata

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2019

A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-Linearity Dynamic VTC.

Kenichi Ohhata

IEEE J. Solid State Circuits, 2019

2018

A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC.

Kenichi Ohhata, Daiki Hayakawa, Kenji Sewaki, Kento Imayanagida, Kouki Ueno, Yuuki Sonoda, Kenichiro Muroya

IEEE Trans. Very Large Scale Integr. Syst., 2018

A 2.3-MW, 950-MHz, 8-Bit Fully-Time-Based Subranging ADC Using Highly-Linear Dynamic VTC.

Kenichi Ohhata

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Low-Power, High-Speed Time-Based Subranging ADCs.

Kenichi Ohhata

Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018

2014

1-GHz, 17.5-mW, 8-bit Subranging ADC Using Offset-Cancelling Charge-Steering Amplifier.

Kenichi Ohhata

IEICE Trans. Electron., 2014

Automatic technique of distortion compensation in resistor ladder for high-speed and low-power ADC.

Wataru Yoshimura, Kenichi Ohhata

IEICE Electron. Express, 2014

Automatic adjustment system for optical interconnection transmitter using improved particle swarm optimization.

Kenichi Ohhata, Hiroki Nakahara, Takuya Inoue, Toru Yazaki, Norio Chujo, Takuma Nishimoto

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2011

A 25 Gb/s 65-nm CMOS Low-Power Laser Diode Driver With Mutually Coupled Peaking Inductors for Optical Interconnects.

Norio Chujo, Toshiaki Takai, Toshiki Sugawara, Yasunobu Matsuoka, Daichi Kawamura, Koichiro Adachi, Tsuneo Kawamata, Tsuneo Ohno, Kenichi Ohhata

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Low-Offset, Low-Power Latched Comparator Using Capacitive Averaging Technique.

Kenichi Ohhata, Hiroki Date, Mai Arita

IEICE Trans. Electron., 2011

2010

17 Gb/s VCSEL driver using double-pulse asymmetric emphasis technique in 90-nm CMOS for optical interconnection.

Kenichi Ohhata, Hironori Imamura, Toshinobu Ohno, Takaya Taniguchi, Kiichi Yamashita, Toru Yazaki, Norio Chujo

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 25Gb/s laser diode driver with mutually coupled peaking inductors for optical interconnects.

Norio Chujo, Tsuneo Kawamata, Kenichi Ohhata, Toshinobu Ohno

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging Architecture.

Kenichi Ohhata, Koki Uchino, Yuichiro Shimizu, Kosuke Oyama, Kiichi Yamashita

IEEE J. Solid State Circuits, 2009

2008

Sandwich Structure Type RF-MEMS Variable Capacitor with Low Voltage Controllability and Wide Tuning Range.

Takuma Nishimoto, Kiichi Yamashita, Kenichi Ohhata

IEICE Trans. Commun., 2008

Feedthrough reduction technique for track-and-hold circuit with body-bias control circuit.

Kenichi Ohhata, Yuichiro Shimizu, Kiichi Yamashita

IEICE Electron. Express, 2008

2007

A 1-GHz, 56.3-dB SFDR CMOS track-and-hold circuit with body-bias control circuit.

Kenichi Ohhata, Kosuke Yayama, Yuichiro Shimizu, Kiichi Yamashita

IEICE Electron. Express, 2007

2006

Design of Low-Noise, Low-Power 10-GHz VCO Using 0.18-µm CMOS Technology.

Kenichi Ohhata, Katsuyoshi Harasawa, Makoto Honda, Kiichi Yamashita

IEICE Trans. Electron., 2006

2005

SiGe-HBT-based 54-gb/s 4: 1 multiplexer IC with full-rate clock for serial communication systems.

Toru Masuda, Kenichi Ohhata, Nobuhiro Shiramizu, Eiji Ohue, Katsuya Oda, Reiko Hayami, Hiromi Shimamoto, Masao Kondo, Takashi Harada, Katsuyoshi Washio

IEEE J. Solid State Circuits, 2005

2000

Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz.

Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kunihiko Yamaguchi, Noriyuki Homma, Atsuo Hotta

IEEE J. Solid State Circuits, 2000

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM.

Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Kunihiko Yamaguchi, Atsuo Hotta, Noriyuki Homma

IEEE J. Solid State Circuits, 2000

1999

Design of a 32.7-GHz bandwidth AGC amplifier IC with wide dynamic range implemented in SiGe HBT.

Kenichi Ohhata, Toru Masuda, Eiji Ohue, Katsuyoshi Washio

IEEE J. Solid State Circuits, 1999

A wide-dynamic-range, high-transimpedance Si bipolar preamplifier IC for 10-Gb/s optical fiber links.

Kenichi Ohhata, Toru Masuda, Kazuo Imai, Ryoji Takeyari, Katsuyoshi Washio

IEEE J. Solid State Circuits, 1999

1996

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry.

Keiichi Higeta, Masami Usami, Masayuki Ohayashi, Yasuhiro Fujimura, Masahiko Nishiyama, Satoru Isomura, Kunihiko Yamaguchi, Youji Idei, Hiroaki Nambu, Kenichi Ohhata, Nadateru Hanta

IEEE J. Solid State Circuits, 1996

1995

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM.

Hiroalu Nambu, Kazuo Kanetani, Youji Idei, Tom Masuda, Keiichi Higeta, Masayuki Ohayashi, Masami Usami, Kunihiko Yamaguchi, Toshiyuki Kikuchi, Takahide Ikeda, Kenichi Ohhata, Takeshi Kusunoki, Noriyuki Homma

IEEE J. Solid State Circuits, April, 1995

1989

An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM.

Kunihiko Yamaguchi, Hiroaki Nanbu, Kazuo Kanetani, Noriyuki Homma, Tohru Nakamura, Kenichi Ohhata, Akihisa Uchida, Katsumi Ogiue

IEEE J. Solid State Circuits, October, 1989